drm/i915/kbl: IPC workaround for kabylake

Display Workarounds #1141
IPC (Isoch Priority Control) may cause underflows.

KBL WA: When IPC is enabled, watermark latency values must be increased
by 4us across all levels. This brings level 0 up to 6us.

Changes since V1:
 - Add Workaround number in commit & code
Changes since V2 (from Paulo):
 - Bikeshed the WA tag so it looks like the others

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161201154940.24446-4-mahesh1.kumar@intel.com

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9ea3eeed3385fbc5857500a7cc01d0d89713f60c..315a1b3392572e8eb2cdada36d4fd04199ed3388 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3596,6 +3596,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
                  fb->modifier == I915_FORMAT_MOD_Yf_TILED;
        x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
 
+       /* Display WA #1141: kbl. */
+       if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
+               latency += 4;
+
        if (apply_memory_bw_wa && x_tiled)
                latency += 15;