drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink

If VRR is enabled, the sink should ignore MSA parameters
and regenerate incoming video stream without depending
on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
bit if VRR is enabled.
Reset this bit on VRR disable.

v2:
* ACtually set the dpcd msa ignore bit (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-13-manasi.d.navare@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 704856b445b10a1ddbfde8d77d7e8068c95dc19f..fbd857f2bdb2633c5f4c982df95e3a89ca7a8b75 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3553,6 +3553,22 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
                return DP_TP_STATUS(encoder->port);
 }
 
+static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
+                                                         const struct intel_crtc_state *crtc_state,
+                                                         bool enable)
+{
+       struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+       if (!crtc_state->vrr.enable)
+               return;
+
+       if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
+                              enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
+               drm_dbg_kms(&i915->drm,
+                           "Failed to set MSA_TIMING_PAR_IGNORE %s in the sink\n",
+                           enable ? "enable" : "disable");
+}
+
 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
                                        const struct intel_crtc_state *crtc_state)
 {
@@ -4351,6 +4367,9 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state,
        /* Disable the decompression in DP Sink */
        intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
                                              false);
+       /* Disable Ignore_MSA bit in DP Sink */
+       intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
+                                                     false);
 }
 
 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2d3396bfc2070a46f0a321c35c00494c2446510e..d5ec8f35e7082d180c1ce5975c8186e84b46be41 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -434,7 +434,7 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
                drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
                                  &rate_select, 1);
 
-       link_config[0] = 0;
+       link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
        link_config[1] = DP_SET_ANSI_8B10B;
        drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);