drm/amd/display: Avoid pipe split when plane is too small

[Why]
The minimum plane size we can support in DML is 16x16. If we try to pass
a 16x16 plane with dynamic pipe split then validation will fail since it
tries to split it into two pipes, each 8x8.

Some userspace doesn't check that the commit fails and because the
commit fails the old state is retained, resulting in corruption.

[How]
Add a workaround to avoid pipe split if any plane is 16x16 or smaller.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 3960a8db94cbe9a937c72d08bfac8ee92ec6f003..1e5a92b192a1528261df979cc3e1fa210670f202 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -690,6 +690,26 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v,
                struct dc_debug_options *dbg,
                struct dc_state *context)
 {
+       int i;
+
+       for (i = 0; i < MAX_PIPES; i++) {
+               struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+               /**
+                * Workaround for avoiding pipe-split in cases where we'd split
+                * planes that are too small, resulting in splits that aren't
+                * valid for the scaler.
+                */
+               if (pipe->plane_state &&
+                   (pipe->plane_state->dst_rect.width <= 16 ||
+                    pipe->plane_state->dst_rect.height <= 16 ||
+                    pipe->plane_state->src_rect.width <= 16 ||
+                    pipe->plane_state->src_rect.height <= 16)) {
+                       hack_disable_optional_pipe_split(v);
+                       return;
+               }
+       }
+
        if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
                hack_disable_optional_pipe_split(v);
 
@@ -702,7 +722,6 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v,
                hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
 }
 
-
 unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev, uint32_t pci_revision_id)
 {
        /* for low power RV2 variants, the highest voltage level we want is 0 */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 4190ee592e6de0fabbe7910ab87b93c6c8c176b3..cef1aa938ab542c397786cb9a8c4671df925a03e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2606,10 +2606,22 @@ int dcn20_validate_apply_pipe_split_flags(
        } else if (dc->debug.force_single_disp_pipe_split)
                        force_split = true;
 
-       /* TODO: fix dc bugs and remove this split threshold thing */
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 
+               /**
+                * Workaround for avoiding pipe-split in cases where we'd split
+                * planes that are too small, resulting in splits that aren't
+                * valid for the scaler.
+                */
+               if (pipe->plane_state &&
+                   (pipe->plane_state->dst_rect.width <= 16 ||
+                    pipe->plane_state->dst_rect.height <= 16 ||
+                    pipe->plane_state->src_rect.width <= 16 ||
+                    pipe->plane_state->src_rect.height <= 16))
+                       avoid_split = true;
+
+               /* TODO: fix dc bugs and remove this split threshold thing */
                if (pipe->stream && !pipe->prev_odm_pipe &&
                                (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
                        ++plane_count;