Rename Neoverse Zeus to Neoverse V1

Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
new file mode 100644 (file)
index 0000000..650eb4d
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_V1_H
+#define NEOVERSE_V1_H
+
+#define NEOVERSE_V1_MIDR                                       U(0x410FD400)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_V1_CPUECTLR_EL1                               S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_V1_CPUPWRCTLR_EL1                             S3_0_C15_C2_7
+#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT              U(1)
+
+#endif /* NEOVERSE_V1_H */

diff --git a/include/lib/cpus/aarch64/neoverse_zeus.h b/include/lib/cpus/aarch64/neoverse_zeus.h
deleted file mode 100644 (file)
index f094727..0000000
--- a/include/lib/cpus/aarch64/neoverse_zeus.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NEOVERSE_ZEUS_H
-#define NEOVERSE_ZEUS_H
-
-#define NEOVERSE_ZEUS_MIDR                                     U(0x410FD400)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions.
- ******************************************************************************/
-#define NEOVERSE_ZEUS_CPUECTLR_EL1                             S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1                           S3_0_C15_C2_7
-#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT            U(1)
-
-#endif /* NEOVERSE_ZEUS_H */

diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
new file mode 100644 (file)
index 0000000..7336294
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <neoverse_v1.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+       /* ---------------------------------------------
+        * HW will do the cache maintenance while powering down
+        * ---------------------------------------------
+        */
+func neoverse_v1_core_pwr_dwn
+       /* ---------------------------------------------
+        * Enable CPU power down bit in power control register
+        * ---------------------------------------------
+        */
+       mrs     x0, NEOVERSE_V1_CPUPWRCTLR_EL1
+       orr     x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+       msr     NEOVERSE_V1_CPUPWRCTLR_EL1, x0
+       isb
+       ret
+endfunc neoverse_v1_core_pwr_dwn
+
+       /*
+        * Errata printing function for Neoverse V1. Must follow AAPCS.
+        */
+#if REPORT_ERRATA
+func neoverse_v1_errata_report
+       ret
+endfunc neoverse_v1_errata_report
+#endif
+
+func neoverse_v1_reset_func
+       mov     x19, x30
+
+       /* Disable speculative loads */
+       msr     SSBS, xzr
+
+       isb
+       ret     x19
+endfunc neoverse_v1_reset_func
+
+       /* ---------------------------------------------
+        * This function provides Neoverse-V1 specific
+        * register information for crash reporting.
+        * It needs to return with x6 pointing to
+        * a list of register names in ascii and
+        * x8 - x15 having values of registers to be
+        * reported.
+        * ---------------------------------------------
+        */
+.section .rodata.neoverse_v1_regs, "aS"
+neoverse_v1_regs:  /* The ascii list of register names to be reported */
+       .asciz  "cpuectlr_el1", ""
+
+func neoverse_v1_cpu_reg_dump
+       adr     x6, neoverse_v1_regs
+       mrs     x8, NEOVERSE_V1_CPUECTLR_EL1
+       ret
+endfunc neoverse_v1_cpu_reg_dump
+
+declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \
+       neoverse_v1_reset_func, \
+       neoverse_v1_core_pwr_dwn

diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_zeus.S
deleted file mode 100644 (file)
index 44882b4..0000000
--- a/lib/cpus/aarch64/neoverse_zeus.S
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <neoverse_zeus.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Neoverse-Zeus supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
-       /* ---------------------------------------------
-        * HW will do the cache maintenance while powering down
-        * ---------------------------------------------
-        */
-func neoverse_zeus_core_pwr_dwn
-       /* ---------------------------------------------
-        * Enable CPU power down bit in power control register
-        * ---------------------------------------------
-        */
-       mrs     x0, NEOVERSE_ZEUS_CPUPWRCTLR_EL1
-       orr     x0, x0, #NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-       msr     NEOVERSE_ZEUS_CPUPWRCTLR_EL1, x0
-       isb
-       ret
-endfunc neoverse_zeus_core_pwr_dwn
-
-       /*
-        * Errata printing function for Neoverse Zeus. Must follow AAPCS.
-        */
-#if REPORT_ERRATA
-func neoverse_zeus_errata_report
-       ret
-endfunc neoverse_zeus_errata_report
-#endif
-
-func neoverse_zeus_reset_func
-       mov     x19, x30
-
-       /* Disable speculative loads */
-       msr     SSBS, xzr
-
-       isb
-       ret     x19
-endfunc neoverse_zeus_reset_func
-
-       /* ---------------------------------------------
-        * This function provides Neoverse-Zeus specific
-        * register information for crash reporting.
-        * It needs to return with x6 pointing to
-        * a list of register names in ascii and
-        * x8 - x15 having values of registers to be
-        * reported.
-        * ---------------------------------------------
-        */
-.section .rodata.neoverse_zeus_regs, "aS"
-neoverse_zeus_regs:  /* The ascii list of register names to be reported */
-       .asciz  "cpuectlr_el1", ""
-
-func neoverse_zeus_cpu_reg_dump
-       adr     x6, neoverse_zeus_regs
-       mrs     x8, NEOVERSE_ZEUS_CPUECTLR_EL1
-       ret
-endfunc neoverse_zeus_cpu_reg_dump
-
-declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \
-       neoverse_zeus_reset_func, \
-       neoverse_zeus_core_pwr_dwn

diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 4b309fd03038a7a65bbcf9e208de6e294f350d7f..4b751fb20f3e4670980fa1590f8fef75284d95bf 100644 (file)
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -61,7 +61,7 @@ else
                                lib/cpus/aarch64/cortex_a78.S           \
                                lib/cpus/aarch64/neoverse_n1.S          \
                                lib/cpus/aarch64/neoverse_e1.S          \
-                               lib/cpus/aarch64/neoverse_zeus.S        \
+                               lib/cpus/aarch64/neoverse_v1.S          \
                                lib/cpus/aarch64/cortex_a78_ae.S        \
                                lib/cpus/aarch64/cortex_a65.S           \
                                lib/cpus/aarch64/cortex_a65ae.S         \

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index f2a2ede8040c9145056a7bf500a01c24b5602a36..4da0d76437227d5546b67df28afd92058ef7b295 100644 (file)
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -120,7 +120,7 @@ else
                                        lib/cpus/aarch64/cortex_a78.S           \
                                        lib/cpus/aarch64/neoverse_n1.S          \
                                        lib/cpus/aarch64/neoverse_e1.S          \
-                                       lib/cpus/aarch64/neoverse_zeus.S        \
+                                       lib/cpus/aarch64/neoverse_v1.S          \
                                        lib/cpus/aarch64/cortex_a78_ae.S        \
                                        lib/cpus/aarch64/cortex_klein.S         \
                                        lib/cpus/aarch64/cortex_matterhorn.S    \

diff --git a/plat/arm/board/rddaniel/platform.mk b/plat/arm/board/rddaniel/platform.mk
index 8909b551ca1debb06cf9a011efd9e400d12ace0b..7422d638a8a64c5a09c06c2520bd61cbd87985a2 100644 (file)
--- a/plat/arm/board/rddaniel/platform.mk
+++ b/plat/arm/board/rddaniel/platform.mk
@@ -12,7 +12,7 @@ RDDANIEL_BASE         =       plat/arm/board/rddaniel
 
 PLAT_INCLUDES          +=      -I${RDDANIEL_BASE}/include/
 
-SGI_CPU_SOURCES                :=      lib/cpus/aarch64/neoverse_zeus.S
+SGI_CPU_SOURCES                :=      lib/cpus/aarch64/neoverse_v1.S
 
 BL1_SOURCES            +=      ${SGI_CPU_SOURCES}                      \
                                ${RDDANIEL_BASE}/rddaniel_err.c

diff --git a/plat/arm/board/rddanielxlr/platform.mk b/plat/arm/board/rddanielxlr/platform.mk
index 61af81aab83fcadba92508222f1a3b58c6eca764..8cbad525c953731f41b7c3acc29b3627fb532f53 100644 (file)
--- a/plat/arm/board/rddanielxlr/platform.mk
+++ b/plat/arm/board/rddanielxlr/platform.mk
@@ -13,7 +13,7 @@ RDDANIELXLR_BASE      =       plat/arm/board/rddanielxlr
 
 PLAT_INCLUDES          +=      -I${RDDANIELXLR_BASE}/include/
 
-SGI_CPU_SOURCES                :=      lib/cpus/aarch64/neoverse_zeus.S
+SGI_CPU_SOURCES                :=      lib/cpus/aarch64/neoverse_v1.S
 
 BL1_SOURCES            +=      ${SGI_CPU_SOURCES}                      \
                                ${RDDANIELXLR_BASE}/rddanielxlr_err.c