riscv: dts: microchip: mpfs: remove bogus card-detect-delay

Recent versions of dt-schema warn about a previously undetected
undocumented property:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: mmc@20008000: Unevaluated properties are not allowed ('card-detect-delay' was unexpected)
        From schema: Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml

There are no GPIOs connected to MSSIO6B4 pin K3 so adding the common
cd-debounce-delay-ms property makes no sense. The Cadence IP has a
register that sets the card detect delay as "DP * tclk". On MPFS, this
clock frequency is not configurable (it must be 200 MHz) & the FPGA
comes out of reset with this register already set.

Fixes: 0df6121fd2c5 ("riscv: dts: microchip: add the sundance polarberry")
Fixes: 6b215eb5b39b ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index ee548ab61a2a582cf2c9784b685286418aeccbee..f3f87ed2007f3cf4b59ccc8b1bd411ab74afa409 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -100,7 +100,6 @@
        disable-wp;
        cap-sd-highspeed;
        cap-mmc-highspeed;
-       card-detect-delay = <200>;
        mmc-ddr-1_8v;
        mmc-hs200-1_8v;
        sd-uhs-sdr12;

diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
index dc11bb8fc8338bc06f15a79baa406408d20320ce..c87cc2d8fe29fa2174bbedca08c272c7331283b8 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
@@ -70,7 +70,6 @@
        disable-wp;
        cap-sd-highspeed;
        cap-mmc-highspeed;
-       card-detect-delay = <200>;
        mmc-ddr-1_8v;
        mmc-hs200-1_8v;
        sd-uhs-sdr12;