drm/amd/pm: Read BIF STRAP also for BACO check

Avoid reading BIF STRAP each time for BACO capability. Read the STRAP
value while checking BACO capability in PPTable.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 1735a96dd307a19a0a10f7bb8637ddaadb694918..5c248accc4a6c98250169063437ca15e9dafb343 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -380,16 +380,31 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
        return 0;
 }
 
-static int arcturus_check_powerplay_table(struct smu_context *smu)
+static void arcturus_check_bxco_support(struct smu_context *smu)
 {
        struct smu_table_context *table_context = &smu->smu_table;
        struct smu_11_0_powerplay_table *powerplay_table =
                table_context->power_play_table;
        struct smu_baco_context *smu_baco = &smu->smu_baco;
+       struct amdgpu_device *adev = smu->adev;
+       uint32_t val;
 
        if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
-           powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
-               smu_baco->platform_support = true;
+           powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
+               val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+               smu_baco->platform_support =
+                       (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
+                                                                       false;
+       }
+}
+
+static int arcturus_check_powerplay_table(struct smu_context *smu)
+{
+       struct smu_table_context *table_context = &smu->smu_table;
+       struct smu_11_0_powerplay_table *powerplay_table =
+               table_context->power_play_table;
+
+       arcturus_check_bxco_support(smu);
 
        table_context->thermal_controller_type =
                powerplay_table->thermal_controller_type;
@@ -2150,13 +2165,11 @@ static void arcturus_get_unique_id(struct smu_context *smu)
 static bool arcturus_is_baco_supported(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
-       uint32_t val;
 
        if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
                return false;
 
-       val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
-       return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+       return true;
 }
 
 static int arcturus_set_df_cstate(struct smu_context *smu,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 78fe13183e8b4d9ee6f0be19deb39dbbe9628929..31e9cc3f3ea085c687fd1c425af3b9ad9f3723d2 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -340,19 +340,34 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
        return 0;
 }
 
-static int navi10_check_powerplay_table(struct smu_context *smu)
+static void navi10_check_bxco_support(struct smu_context *smu)
 {
        struct smu_table_context *table_context = &smu->smu_table;
        struct smu_11_0_powerplay_table *powerplay_table =
                table_context->power_play_table;
        struct smu_baco_context *smu_baco = &smu->smu_baco;
+       struct amdgpu_device *adev = smu->adev;
+       uint32_t val;
+
+       if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
+           powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
+               val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+               smu_baco->platform_support =
+                       (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
+                                                                       false;
+       }
+}
+
+static int navi10_check_powerplay_table(struct smu_context *smu)
+{
+       struct smu_table_context *table_context = &smu->smu_table;
+       struct smu_11_0_powerplay_table *powerplay_table =
+               table_context->power_play_table;
 
        if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
                smu->dc_controlled_by_gpio = true;
 
-       if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
-           powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
-               smu_baco->platform_support = true;
+       navi10_check_bxco_support(smu);
 
        table_context->thermal_controller_type =
                powerplay_table->thermal_controller_type;
@@ -2245,13 +2260,11 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
 static bool navi10_is_baco_supported(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
-       uint32_t val;
 
        if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
                return false;
 
-       val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
-       return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+       return true;
 }
 
 static int navi10_set_default_od_settings(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 75acdb80c4990d44dea0f7a3f78689341cf627f1..6614dbb723bed0c58bee11f3bd9af96a4ae25fec 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -323,19 +323,34 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
        return 0;
 }
 
-static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
+static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
 {
        struct smu_table_context *table_context = &smu->smu_table;
        struct smu_11_0_7_powerplay_table *powerplay_table =
                table_context->power_play_table;
        struct smu_baco_context *smu_baco = &smu->smu_baco;
+       struct amdgpu_device *adev = smu->adev;
+       uint32_t val;
+
+       if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
+           powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) {
+               val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+               smu_baco->platform_support =
+                       (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
+                                                                       false;
+       }
+}
+
+static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
+{
+       struct smu_table_context *table_context = &smu->smu_table;
+       struct smu_11_0_7_powerplay_table *powerplay_table =
+               table_context->power_play_table;
 
        if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
                smu->dc_controlled_by_gpio = true;
 
-       if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
-           powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
-               smu_baco->platform_support = true;
+       sienna_cichlid_check_bxco_support(smu);
 
        table_context->thermal_controller_type =
                powerplay_table->thermal_controller_type;
@@ -2088,13 +2103,11 @@ static int sienna_cichlid_run_btc(struct smu_context *smu)
 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
-       uint32_t val;
 
        if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
                return false;
 
-       val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
-       return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+       return true;
 }
 
 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)