sunxi: f1c100s: Fix FEL registers restore

Commit 43c64ebcb24f ("arm: arm926ej-s: Add sunxi code") introduced
the ARM926 version of the code to save and restore some FEL state, to
be able to return to the BROM FEL code after the SPL has run.

However during review a change was made, that happened to mess up the
register restore part, so SCTLR and CPSR ended up with the wrong values,
breaking return to FEL.

Use the same offset that we actually save those registers to, to make
FEL booting actually work on the Lichee Pi Nano.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
index 08be7ed11aa0664d64ffe9e49fad752c7e5455e4..25924033c63da0c7e7c82382adecf4e3f5232eaa 100644 (file)
--- a/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
+++ b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S
@@ -25,9 +25,9 @@ ENTRY(return_to_fel)
        mov     sp, r0
        mov     lr, r1
        ldr     r0, =fel_stash
-       ldr     r1, [r0, #16]
-       mcr     p15, 0, r1, c1, c0, 0   @ Write CP15 Control Register
        ldr     r1, [r0, #12]
+       mcr     p15, 0, r1, c1, c0, 0   @ Write CP15 SCTLR register
+       ldr     r1, [r0, #8]
        msr     cpsr, r1                @ Write CPSR
        bx      lr
 ENDPROC(return_to_fel)