drm/amdgpu: check GFX RAS capability before reset counters

disallow the logical to be enabled on platforms that
don't support gfx ras at this stage, like sriov skus,
dgpu with legacy ras.etc

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1081fa3d4b0f44ba389442a251b6fa0ded555b86..3d7318abe57f3fef19f60497ee38e4e0b8d7be46 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -6306,6 +6306,9 @@ static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev)
 {
        int i, j, k;
 
+       if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
+               return;
+
        /* read back registers to clear the counters */
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
index 17f1e7b69a60350c73a7474a5c1eb216c6e5e20a..cceb46faf212abe5f4446742801849bf41505638 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
@@ -897,6 +897,9 @@ void gfx_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
 {
        int i, j, k;
 
+       if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
+               return;
+
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {
                for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {