mediatek: mt8192: dcm: Add mcusys related dcm drivers

1. Add mcusys related dcm drivers
2. Turn on mcusys-related dcm by default

Change-Id: Ibbee37c87cc38e7a6cd7c93c2fc0817aad6dbe95
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>

diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c
index 2a0e131b94ff23d1516ccdc55d78fc88c41f7a6d..32e124f1f556ddb03f1ea36352f5e91f247a69cd 100644 (file)
--- a/plat/mediatek/mt8192/bl31_plat_setup.c
+++ b/plat/mediatek/mt8192/bl31_plat_setup.c
@@ -19,6 +19,7 @@
 #include <gpio/mtgpio.h>
 #include <mt_gic_v3.h>
 #include <mt_timer.h>
+#include <mtk_dcm.h>
 #include <plat_params.h>
 #include <plat_private.h>
 
@@ -83,6 +84,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
  ******************************************************************************/
 void bl31_platform_setup(void)
 {
+       /* Set dcm on */
+       if (!dcm_set_default()) {
+               ERROR("Failed to set default dcm on!!\n");
+       }
+
        /* Initialize the GIC driver, CPU and distributor interfaces */
        mt_gic_driver_init();
        mt_gic_init();

diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c
new file mode 100644 (file)
index 0000000..dd8bf4e
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_dcm.h>
+#include <mtk_dcm_utils.h>
+
+static void dcm_armcore(bool mode)
+{
+       dcm_mp_cpusys_top_bus_pll_div_dcm(mode);
+       dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode);
+       dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode);
+}
+
+static void dcm_mcusys(bool on)
+{
+       dcm_mp_cpusys_top_adb_dcm(on);
+       dcm_mp_cpusys_top_apb_dcm(on);
+       dcm_mp_cpusys_top_cpubiu_dcm(on);
+       dcm_mp_cpusys_top_misc_dcm(on);
+       dcm_mp_cpusys_top_mp0_qdcm(on);
+       dcm_cpccfg_reg_emi_wfifo(on);
+       dcm_mp_cpusys_top_last_cor_idle_dcm(on);
+}
+
+static void dcm_stall(bool on)
+{
+       dcm_mp_cpusys_top_core_stall_dcm(on);
+       dcm_mp_cpusys_top_fcm_stall_dcm(on);
+}
+
+static bool check_dcm_state(void)
+{
+       bool ret = true;
+
+       ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on();
+       ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on();
+       ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on();
+
+       ret &= dcm_mp_cpusys_top_adb_dcm_is_on();
+       ret &= dcm_mp_cpusys_top_apb_dcm_is_on();
+       ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on();
+       ret &= dcm_mp_cpusys_top_misc_dcm_is_on();
+       ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on();
+       ret &= dcm_cpccfg_reg_emi_wfifo_is_on();
+       ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on();
+
+       ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on();
+       ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on();
+
+       return ret;
+}
+
+bool dcm_set_default(void)
+{
+       dcm_armcore(true);
+       dcm_mcusys(true);
+       dcm_stall(true);
+
+       return check_dcm_state();
+}

diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h
new file mode 100644 (file)
index 0000000..ee98d0e
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_DCM_H
+#define MTK_DCM_H
+
+#include <stdbool.h>
+
+bool dcm_set_default(void);
+
+#endif /* #ifndef MTK_DCM_H */

diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c
new file mode 100644 (file)
index 0000000..15a700c
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c
@@ -0,0 +1,562 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mtk_dcm_utils.h>
+
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \
+                       BIT(16) | \
+                       BIT(17) | \
+                       BIT(18) | \
+                       BIT(21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \
+                       BIT(16) | \
+                       BIT(17) | \
+                       BIT(18))
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | \
+                       BIT(16) | \
+                       BIT(17) | \
+                       BIT(18) | \
+                       BIT(21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | \
+                       BIT(16) | \
+                       BIT(17) | \
+                       BIT(18))
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \
+                       (0x0 << 16) | \
+                       (0x0 << 17) | \
+                       (0x0 << 18) | \
+                       (0x0 << 21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \
+                       (0x0 << 16) | \
+                       (0x0 << 17) | \
+                       (0x0 << 18))
+
+bool dcm_mp_cpusys_top_adb_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(MP_ADB_DCM_CFG0) &
+               MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
+       ret &= ((mmio_read_32(MP_ADB_DCM_CFG4) &
+               MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
+       ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) &
+               MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_adb_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */
+               mmio_clrsetbits_32(MP_ADB_DCM_CFG0,
+                       MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
+               mmio_clrsetbits_32(MP_ADB_DCM_CFG4,
+                       MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
+                       MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
+               mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
+                       MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
+                       MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */
+               mmio_clrsetbits_32(MP_ADB_DCM_CFG0,
+                       MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_ADB_DCM_REG0_OFF);
+               mmio_clrsetbits_32(MP_ADB_DCM_CFG4,
+                       MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
+                       MP_CPUSYS_TOP_ADB_DCM_REG1_OFF);
+               mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
+                       MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
+                       MP_CPUSYS_TOP_ADB_DCM_REG2_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16))
+#define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16))
+#define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16))
+
+bool dcm_mp_cpusys_top_apb_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
+               MP_CPUSYS_TOP_APB_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON);
+       ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) &
+               MP_CPUSYS_TOP_APB_DCM_REG1_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON);
+       ret &= ((mmio_read_32(MP0_DCM_CFG0) &
+               MP_CPUSYS_TOP_APB_DCM_REG2_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_apb_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */
+               mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+                       MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_APB_DCM_REG0_ON);
+               mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
+                       MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
+                       MP_CPUSYS_TOP_APB_DCM_REG1_ON);
+               mmio_clrsetbits_32(MP0_DCM_CFG0,
+                       MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
+                       MP_CPUSYS_TOP_APB_DCM_REG2_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */
+               mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+                       MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_APB_DCM_REG0_OFF);
+               mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
+                       MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
+                       MP_CPUSYS_TOP_APB_DCM_REG1_OFF);
+               mmio_clrsetbits_32(MP0_DCM_CFG0,
+                       MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
+                       MP_CPUSYS_TOP_APB_DCM_REG2_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(BUS_PLLDIV_CFG) &
+               MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
+               mmio_clrsetbits_32(BUS_PLLDIV_CFG,
+                       MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
+               mmio_clrsetbits_32(BUS_PLLDIV_CFG,
+                       MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0))
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0))
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0))
+
+bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(MP0_DCM_CFG7) &
+               MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_core_stall_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */
+               mmio_clrsetbits_32(MP0_DCM_CFG7,
+                       MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */
+               mmio_clrsetbits_32(MP0_DCM_CFG7,
+                       MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0))
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0))
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0))
+
+bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(MCSI_DCM0) &
+               MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_cpubiu_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */
+               mmio_clrsetbits_32(MCSI_DCM0,
+                       MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */
+               mmio_clrsetbits_32(MCSI_DCM0,
+                       MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(CPU_PLLDIV_CFG0) &
+               MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
+               mmio_clrsetbits_32(CPU_PLLDIV_CFG0,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
+               mmio_clrsetbits_32(CPU_PLLDIV_CFG0,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(CPU_PLLDIV_CFG1) &
+               MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
+               mmio_clrsetbits_32(CPU_PLLDIV_CFG1,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
+               mmio_clrsetbits_32(CPU_PLLDIV_CFG1,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(CPU_PLLDIV_CFG2) &
+               MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */
+               mmio_clrsetbits_32(CPU_PLLDIV_CFG2,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */
+               mmio_clrsetbits_32(CPU_PLLDIV_CFG2,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(CPU_PLLDIV_CFG3) &
+               MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */
+               mmio_clrsetbits_32(CPU_PLLDIV_CFG3,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */
+               mmio_clrsetbits_32(CPU_PLLDIV_CFG3,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(CPU_PLLDIV_CFG4) &
+               MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */
+               mmio_clrsetbits_32(CPU_PLLDIV_CFG4,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */
+               mmio_clrsetbits_32(CPU_PLLDIV_CFG4,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4))
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4))
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4))
+
+bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(MP0_DCM_CFG7) &
+               MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_fcm_stall_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */
+               mmio_clrsetbits_32(MP0_DCM_CFG7,
+                       MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */
+               mmio_clrsetbits_32(MP0_DCM_CFG7,
+                       MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1U << 31))
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1U << 31))
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0U << 31))
+
+bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(BUS_PLLDIV_CFG) &
+               MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
+               mmio_clrsetbits_32(BUS_PLLDIV_CFG,
+                       MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
+               mmio_clrsetbits_32(BUS_PLLDIV_CFG,
+                       MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | \
+                       BIT(4))
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | \
+                       BIT(4))
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \
+                       (0x0 << 4))
+
+bool dcm_mp_cpusys_top_misc_dcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
+               MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_misc_dcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */
+               mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+                       MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */
+               mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+                       MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
+                       MP_CPUSYS_TOP_MISC_DCM_REG0_OFF);
+       }
+}
+
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | \
+                       BIT(1) | \
+                       BIT(2) | \
+                       BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | \
+                       BIT(1) | \
+                       BIT(2) | \
+                       BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \
+                       (0x0 << 1) | \
+                       (0x0 << 2) | \
+                       (0x0 << 3))
+
+bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
+               MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
+       ret &= ((mmio_read_32(MP0_DCM_CFG0) &
+               MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) ==
+               (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
+
+       return ret;
+}
+
+void dcm_mp_cpusys_top_mp0_qdcm(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */
+               mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+                       MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
+                       MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
+               mmio_clrsetbits_32(MP0_DCM_CFG0,
+                       MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
+                       MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */
+               mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+                       MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
+                       MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF);
+               mmio_clrsetbits_32(MP0_DCM_CFG0,
+                       MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
+                       MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF);
+       }
+}
+
+#define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | \
+                       BIT(1) | \
+                       BIT(2) | \
+                       BIT(3))
+#define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | \
+                       BIT(1) | \
+                       BIT(2) | \
+                       BIT(3))
+#define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \
+                       (0x0 << 1) | \
+                       (0x0 << 2) | \
+                       (0x0 << 3))
+
+bool dcm_cpccfg_reg_emi_wfifo_is_on(void)
+{
+       bool ret = true;
+
+       ret &= ((mmio_read_32(EMI_WFIFO) &
+               CPCCFG_REG_EMI_WFIFO_REG0_MASK) ==
+               (unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON);
+
+       return ret;
+}
+
+void dcm_cpccfg_reg_emi_wfifo(bool on)
+{
+       if (on) {
+               /* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */
+               mmio_clrsetbits_32(EMI_WFIFO,
+                       CPCCFG_REG_EMI_WFIFO_REG0_MASK,
+                       CPCCFG_REG_EMI_WFIFO_REG0_ON);
+       } else {
+               /* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */
+               mmio_clrsetbits_32(EMI_WFIFO,
+                       CPCCFG_REG_EMI_WFIFO_REG0_MASK,
+                       CPCCFG_REG_EMI_WFIFO_REG0_OFF);
+       }
+}
+

diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h
new file mode 100644 (file)
index 0000000..1cf7834
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_DCM_UTILS_H
+#define MTK_DCM_UTILS_H
+
+#include <stdbool.h>
+
+#include <mtk_dcm.h>
+#include <platform_def.h>
+
+/* Base */
+#define MP_CPUSYS_TOP_BASE     (MCUCFG_BASE + 0x8000)
+#define CPCCFG_REG_BASE                (MCUCFG_BASE + 0xA800)
+
+/* Register Definition */
+#define CPU_PLLDIV_CFG0                (MP_CPUSYS_TOP_BASE + 0x22a0)
+#define CPU_PLLDIV_CFG1                (MP_CPUSYS_TOP_BASE + 0x22a4)
+#define CPU_PLLDIV_CFG2                (MP_CPUSYS_TOP_BASE + 0x22a8)
+#define CPU_PLLDIV_CFG3                (MP_CPUSYS_TOP_BASE + 0x22ac)
+#define CPU_PLLDIV_CFG4                (MP_CPUSYS_TOP_BASE + 0x22b0)
+#define BUS_PLLDIV_CFG         (MP_CPUSYS_TOP_BASE + 0x22e0)
+#define MCSI_DCM0              (MP_CPUSYS_TOP_BASE + 0x2440)
+#define MP_ADB_DCM_CFG0                (MP_CPUSYS_TOP_BASE + 0x2500)
+#define MP_ADB_DCM_CFG4                (MP_CPUSYS_TOP_BASE + 0x2510)
+#define MP_MISC_DCM_CFG0       (MP_CPUSYS_TOP_BASE + 0x2518)
+#define MCUSYS_DCM_CFG0                (MP_CPUSYS_TOP_BASE + 0x25c0)
+#define EMI_WFIFO              (CPCCFG_REG_BASE + 0x100)
+#define MP0_DCM_CFG0           (MP_CPUSYS_TOP_BASE + 0x4880)
+#define MP0_DCM_CFG7           (MP_CPUSYS_TOP_BASE + 0x489c)
+
+/* MP_CPUSYS_TOP */
+bool dcm_mp_cpusys_top_adb_dcm_is_on(void);
+void dcm_mp_cpusys_top_adb_dcm(bool on);
+bool dcm_mp_cpusys_top_apb_dcm_is_on(void);
+void dcm_mp_cpusys_top_apb_dcm(bool on);
+bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void);
+void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on);
+bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void);
+void dcm_mp_cpusys_top_core_stall_dcm(bool on);
+bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpubiu_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(bool on);
+bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void);
+void dcm_mp_cpusys_top_fcm_stall_dcm(bool on);
+bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void);
+void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on);
+bool dcm_mp_cpusys_top_misc_dcm_is_on(void);
+void dcm_mp_cpusys_top_misc_dcm(bool on);
+bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void);
+void dcm_mp_cpusys_top_mp0_qdcm(bool on);
+/* CPCCFG_REG */
+bool dcm_cpccfg_reg_emi_wfifo_is_on(void);
+void dcm_cpccfg_reg_emi_wfifo(bool on);
+
+#endif

diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index b36a7e867ee5c1095f9b13c29b6b8d94311546bf..191895a21e65ba0ce7b222cfe5bb3a0769856a7d 100644 (file)
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -10,6 +10,7 @@ MTK_PLAT_SOC  := ${MTK_PLAT}/${PLAT}
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
                  -I${MTK_PLAT_SOC}/include/                       \
                  -I${MTK_PLAT_SOC}/drivers/                       \
+                 -I${MTK_PLAT_SOC}/drivers/dcm                    \
                  -I${MTK_PLAT_SOC}/drivers/gpio/                  \
                  -I${MTK_PLAT_SOC}/drivers/mcdi/                  \
                  -I${MTK_PLAT_SOC}/drivers/pmic/                  \
@@ -50,6 +51,8 @@ BL31_SOURCES    += common/desc_image_load.c                              \
                    ${MTK_PLAT_SOC}/plat_mt_gic.c                         \
                    ${MTK_PLAT_SOC}/plat_mt_cirq.c                        \
                    ${MTK_PLAT_SOC}/plat_sip_calls.c                      \
+                   ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c                 \
+                   ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c           \
                    ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
                    ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c              \
                    ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c          \