drm/i915/gem: Specify address type for chained reloc batches

It is required that a chained batch be in the same address domain as its
parent, and also that must be specified in the command for earlier gen
as it is not inferred from the chaining until gen6.

Fixes: f57e6886513f ("drm/i915/gem: Use chained reloc batches")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200504125149.4396-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index cce7df231cb91df218353f0443dc2ba8543c3dc3..1c247ad0971a20f456d0663ab36e021c388a2ff0 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1004,14 +1004,14 @@ static int reloc_gpu_chain(struct reloc_cache *cache)
        GEM_BUG_ON(cache->rq_size + RELOC_TAIL > PAGE_SIZE  / sizeof(u32));
        cmd = cache->rq_cmd + cache->rq_size;
        *cmd++ = MI_ARB_CHECK;
-       if (cache->gen >= 8) {
+       if (cache->gen >= 8)
                *cmd++ = MI_BATCH_BUFFER_START_GEN8;
-               *cmd++ = lower_32_bits(batch->node.start);
-               *cmd++ = upper_32_bits(batch->node.start);
-       } else {
+       else if (cache->gen >= 6)
                *cmd++ = MI_BATCH_BUFFER_START;
-               *cmd++ = lower_32_bits(batch->node.start);
-       }
+       else
+               *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
+       *cmd++ = lower_32_bits(batch->node.start);
+       *cmd++ = upper_32_bits(batch->node.start); /* Always 0 for gen<8 */
        i915_gem_object_flush_map(cache->rq_vma->obj);
        i915_gem_object_unpin_map(cache->rq_vma->obj);
        cache->rq_vma = NULL;