LoongArch: Add writecombine support for drm

LoongArch maintains cache coherency in hardware, but its WUC attribute
(Weak-ordered UnCached, which is similar to WC) is out of the scope of
cache coherency machanism. This means WUC can only used for write-only
memory regions.

Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
index e957d4851dc060ebef650f007418529b3ab1673d..f024dc93939ef3d696ac9c720fe87166223e5a1b 100644 (file)
--- a/drivers/gpu/drm/drm_vm.c
+++ b/drivers/gpu/drm/drm_vm.c
@@ -69,7 +69,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *map,
        pgprot_t tmp = vm_get_page_prot(vma->vm_flags);
 
 #if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \
-    defined(__mips__)
+    defined(__mips__) || defined(__loongarch__)
        if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING))
                tmp = pgprot_noncached(tmp);
        else

diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
index a3ad7c9736ec461085bca19661df44fe9add6824..b3fffe7b5062a9dd076a09d5b6099023006f19a3 100644 (file)
--- a/drivers/gpu/drm/ttm/ttm_module.c
+++ b/drivers/gpu/drm/ttm/ttm_module.c
@@ -74,7 +74,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
 #endif /* CONFIG_UML */
 #endif /* __i386__ || __x86_64__ */
 #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
-       defined(__powerpc__) || defined(__mips__)
+       defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
        if (caching == ttm_write_combined)
                tmp = pgprot_writecombine(tmp);
        else

diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index 22deb216b59c0dce9a576b713d1a289e6c30754e..08e0e3ffad1319d8a32a21b37e1b070ae0a9acaa 100644 (file)
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void)
         * optimization entirely for ARM and arm64.
         */
        return false;
+#elif defined(CONFIG_LOONGARCH)
+       /*
+        * LoongArch maintains cache coherency in hardware, but its WUC attribute
+        * (Weak-ordered UnCached, which is similar to WC) is out of the scope of
+        * cache coherency machanism. This means WUC can only used for write-only
+        * memory regions.
+        */
+       return false;
 #else
        return true;
 #endif