config HAS_FSL_DR_USB
def_bool y
depends on USB_EHCI_HCD && PPC
+
+config SYS_DPAA_FMAN
+ bool
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT
+ select SYS_DPAA_FMAN
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT
+ select SYS_DPAA_FMAN
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
* mux 2 clock for LS1043A/LS1046A.
*/
-#if defined(CONFIG_SYS_DPAA_FMAN) || \
- defined(CONFIG_ARCH_LS1046A) || \
- defined(CONFIG_ARCH_LS1043A)
- u32 rcw_tmp;
-#endif
+ __maybe_unused u32 rcw_tmp;
struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
#define HWA_CGA_M1_CLK_SEL 0xe0000000
#define HWA_CGA_M1_CLK_SHIFT 29
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
rcw_tmp = in_be32(&gur->rcwsr[7]);
switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
case 2:
/* setup general icid offsets */
set_icid(icid_tbl, icid_tbl_sz);
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
#endif
}
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
bool "Support kmcent2"
select VENDOR_KM
select FSL_CORENET
+ select SYS_DPAA_FMAN
+ select SYS_DPAA_PME
select SYS_L3_SIZE_256KB
endchoice
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_FMAN
+ select SYS_DPAA_PME
+ select SYS_DPAA_RMAN
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
select SYS_FSL_ERRATUM_A005275
select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_FMAN
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_FMAN
+ select SYS_DPAA_PME
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_FMAN
+ select SYS_DPAA_PME
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_DCE if !NOBQFMAN
+ select SYS_DPAA_FMAN if !NOBQFMAN
+ select SYS_DPAA_PME if !NOBQFMAN
+ select SYS_DPAA_RMAN if !NOBQFMAN
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
+ select SYS_PMAN if !NOBQFMAN
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_DCE if !NOBQFMAN
+ select SYS_DPAA_FMAN if !NOBQFMAN
+ select SYS_DPAA_PME if !NOBQFMAN
+ select SYS_DPAA_RMAN if !NOBQFMAN
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468
select SYS_FSL_ERRATUM_A005871
select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
+ select SYS_PMAN if !NOBQFMAN
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
help
Enable PowerPC E6500 core
+config NOBQFMAN
+ bool
+
config FSL_LAW
bool
help
if changed by pre-boot regime. The value here must match
the current value in SoC. If not sure, do not change.
+config SYS_DPAA_PME
+ bool
+
+config SYS_DPAA_DCE
+ bool
+
+config SYS_DPAA_RMAN
+ bool
+
config A003399_NOR_WORKAROUND
bool
help
config FSL_PCIE_RESET
bool
+config SYS_PMAN
+ bool
+
config SYS_FSL_RAID_ENGINE
bool
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_SYS_DPAA_RMAN /* RMan */
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_FMAN_ENET
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN /* RMan */
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN /* RMan */
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-
/* Qman / Bman */
/* RGMII (FM1@DTESC5) is local managemant interface */
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
/* FMan ucode */
#ifndef SPL_NO_FMAN
-#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#endif
/* FMan ucode */
#ifndef SPL_NO_FMAN
-#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#endif