drm/amd/display: check actual clock value.

[Why]
Actual dpp/disp clock PMFW set are always equal or more than requested.
Need to cache the actual clock for debugging purpose.

[How]
Add actuall dpp/disp clk in clock manager and save it when set clocks.
Add an ASSERT in case of actual clock less than requested.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index f30f3fdba433ebb83aabaf7d03fcbfff3e53d7b5..ec394e3d8367bf18b2d780c1873ba42e1d562eca 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -170,7 +170,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 
        if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
                clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
-               rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
+               clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 
                update_dispclk = true;
        }
@@ -178,11 +178,14 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
        if (dpp_clock_lowered) {
                // increase per DPP DTO before lowering global dppclk
                dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
-               rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+               clk_mgr_base->clks.actual_dppclk_khz =
+                               rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+
        } else {
                // increase global DPPCLK before lowering per DPP DTO
                if (update_dppclk || update_dispclk)
-                       rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+                       clk_mgr_base->clks.actual_dppclk_khz =
+                                       rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
                // always update dtos unless clock is lowered and not safe to lower
                if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
                        dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 9a374522e9631d4be3ac29e0a7f3b2040e1dd856..ab2b9c61e5655c27ad0c2dea5dc3155677ebc811 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -136,6 +136,10 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis
                }
        }
 
+       // pmfw always set clock more than or equal requested clock
+       if (!IS_DIAG_DC(dc->ctx->dce_environment))
+               ASSERT(actual_dispclk_set_mhz >= requested_dispclk_khz / 1000);
+
        return actual_dispclk_set_mhz * 1000;
 }
 
@@ -194,12 +198,16 @@ void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phy
 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
 {
        int actual_dppclk_set_mhz = -1;
+       struct dc *dc = clk_mgr->base.ctx->dc;
 
        actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
                        clk_mgr,
                        VBIOSSMC_MSG_SetDppclkFreq,
                        requested_dpp_khz / 1000);
 
+       if (!IS_DIAG_DC(dc->ctx->dce_environment))
+               ASSERT(actual_dppclk_set_mhz >= requested_dpp_khz / 1000);
+
        return actual_dppclk_set_mhz * 1000;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5cf0b988c9c3680ce40ab9696aad8e854706d967..4c57cf099b5e50f95d2e356bd68f0aedbcd3701b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -342,7 +342,9 @@ enum dcn_pwr_state {
  */
 struct dc_clocks {
        int dispclk_khz;
+       int actual_dispclk_khz;
        int dppclk_khz;
+       int actual_dppclk_khz;
        int disp_dpp_voltage_level_khz;
        int dcfclk_khz;
        int socclk_khz;