riscv: Enable LOCKDEP_SUPPORT & fixup TRACE_IRQFLAGS_SUPPORT

Lockdep is needed by proving the spinlocks and rwlocks. To suupport
it, we need fixup TRACE_IRQFLAGS_SUPPORT in kernel/entry.S. This
patch follow Documentation/irqflags-tracing.txt.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 089293e4ad46d3a54952290de45c70659ebe7349..543335df7376f1e59fd6c2dfc23e650bed27bbe1 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -179,6 +179,9 @@ config PGTABLE_LEVELS
        default 3 if 64BIT
        default 2
 
+config LOCKDEP_SUPPORT
+       def_bool y
+
 source "arch/riscv/Kconfig.socs"
 
 menu "Platform type"

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index cae7e6d4c7ef10593d095d2cf976c65e7dc3ebdb..45c81e49462d5a0a078fe22253e47206b50f09f2 100644 (file)
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -97,19 +97,26 @@ _save_context:
        la gp, __global_pointer$
 .option pop
 
-       la ra, ret_from_exception
+#ifdef CONFIG_TRACE_IRQFLAGS
+       call trace_hardirqs_off
+#endif
        /*
         * MSB of cause differentiates between
         * interrupts and exceptions
         */
        bge s4, zero, 1f
 
+       la ra, ret_from_exception
+
        /* Handle interrupts */
        move a0, sp /* pt_regs */
        la a1, handle_arch_irq
        REG_L a1, (a1)
        jr a1
 1:
+#ifdef CONFIG_TRACE_IRQFLAGS
+       call trace_hardirqs_on
+#endif
        /*
         * Exceptions run with interrupts enabled or disabled depending on the
         * state of SR_PIE in m/sstatus.
@@ -119,6 +126,7 @@ _save_context:
        csrs CSR_STATUS, SR_IE
 
 1:
+       la ra, ret_from_exception
        /* Handle syscalls */
        li t0, EXC_SYSCALL
        beq s4, t0, handle_syscall
@@ -137,6 +145,17 @@ _save_context:
        tail do_trap_unknown
 
 handle_syscall:
+#ifdef CONFIG_TRACE_IRQFLAGS
+       /* Recover a0 - a7 for system calls */
+       REG_L a0, PT_A0(sp)
+       REG_L a1, PT_A1(sp)
+       REG_L a2, PT_A2(sp)
+       REG_L a3, PT_A3(sp)
+       REG_L a4, PT_A4(sp)
+       REG_L a5, PT_A5(sp)
+       REG_L a6, PT_A6(sp)
+       REG_L a7, PT_A7(sp)
+#endif
         /* save the initial A0 value (needed in signal handlers) */
        REG_S a0, PT_ORIG_A0(sp)
        /*
@@ -190,6 +209,9 @@ ret_from_syscall_rejected:
 ret_from_exception:
        REG_L s0, PT_STATUS(sp)
        csrc CSR_STATUS, SR_IE
+#ifdef CONFIG_TRACE_IRQFLAGS
+       call trace_hardirqs_off
+#endif
 #ifdef CONFIG_RISCV_M_MODE
        /* the MPP value is too large to be used as an immediate arg for addi */
        li t0, SR_MPP
@@ -216,6 +238,16 @@ resume_userspace:
        csrw CSR_SCRATCH, tp
 
 restore_all:
+#ifdef CONFIG_TRACE_IRQFLAGS
+       REG_L s1, PT_STATUS(sp)
+       andi t0, s1, SR_PIE
+       beqz t0, 1f
+       call trace_hardirqs_on
+       j 2f
+1:
+       call trace_hardirqs_off
+2:
+#endif
        REG_L a0, PT_STATUS(sp)
        /*
         * The current load reservation is effectively part of the processor's