]> git.baikalelectronics.ru Git - kernel.git/commitdiff
ARM: dts: bcm: HR2: Fix PPI interrupt types
authorHamish Martin <hamish.martin@alliedtelesis.co.nz>
Wed, 20 May 2020 04:30:42 +0000 (16:30 +1200)
committerFlorian Fainelli <f.fainelli@gmail.com>
Thu, 21 May 2020 00:15:16 +0000 (17:15 -0700)
These error messages are output when booting on a BCM HR2 system:
    GIC: PPI11 is secure or misconfigured
    GIC: PPI13 is secure or misconfigured

Per ARM documentation these interrupts are triggered on a rising edge.
See ARM Cortex A-9 MPCore Technical Reference Manual, Revision r4p1,
Section 3.3.8 Interrupt Configuration Registers.

The same issue was resolved for NSP systems in commit 466e37e67260
("ARM: dts: NSP: Fix PPI interrupt types").

Fixes: bcb9f07b56fc ("ARM: dts: Add Broadcom Hurricane 2 DTS include file")
Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
arch/arm/boot/dts/bcm-hr2.dtsi

index 6142c672811e510f416d3c0cfca2b417d3c03c25..5e5f5ca3c86f1654e457b0608faf0b3985b7babc 100644 (file)
@@ -75,7 +75,7 @@
                timer@20200 {
                        compatible = "arm,cortex-a9-global-timer";
                        reg = <0x20200 0x100>;
-                       interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
                        clocks = <&periph_clk>;
                };
 
@@ -83,7 +83,7 @@
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0x20600 0x20>;
                        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
-                                                 IRQ_TYPE_LEVEL_HIGH)>;
+                                                 IRQ_TYPE_EDGE_RISING)>;
                        clocks = <&periph_clk>;
                };
 
@@ -91,7 +91,7 @@
                        compatible = "arm,cortex-a9-twd-wdt";
                        reg = <0x20620 0x20>;
                        interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
-                                                 IRQ_TYPE_LEVEL_HIGH)>;
+                                                 IRQ_TYPE_EDGE_RISING)>;
                        clocks = <&periph_clk>;
                };