drm/i915/bxt+: Enable IPC support

This patch adds IPC support. This patch also enables IPC in all supported
platforms based on has_ipc flag.
IPC (Isochronous Priority Control) is the hardware feature, which
dynamically controls the memory read priority of Display.

When IPC is enabled, plane read requests are sent at high priority until
filling above the transition watermark, then the requests are sent at
lower priority until dropping below the level 0 watermark.
The lower priority requests allow other memory clients to have better
memory access. When IPC is disabled, all plane read requests are sent at
high priority.

Changes since V1:
 - Remove commandline parameter to disable ipc
 - Address Paulo's comments
Changes since V2:
 - Address review comments
 - Set ipc_enabled flag
Changes since V3:
 - move ipc_enabled flag assignment inside intel_ipc_enable function
Changes since V4:
 - Re-enable IPC after suspend/resume
Changes since V5:
 - Enable IPC for all gen >=9 except SKL
Changes since V6:
 - fix commit msg
 - after resume program IPC based on SW state.
Changes since V7:
 - Modify IPC support check based on HAS_IPC macro (suggested by Chris)

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170817134529.2839-8-mahesh1.kumar@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ff70fc45ba7c57b30f0a4141a12168e124e164bd..5c111ea96e808089ef90991593f714abd86bf5e0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1341,7 +1341,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 
        intel_runtime_pm_enable(dev_priv);
 
-       dev_priv->ipc_enabled = false;
+       intel_init_ipc(dev_priv);
 
        if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
                DRM_INFO("DRM_I915_DEBUG enabled\n");
@@ -2609,6 +2609,8 @@ static int intel_runtime_resume(struct device *kdev)
        if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
                intel_hpd_init(dev_priv);
 
+       intel_enable_ipc(dev_priv);
+
        enable_rpm_wakeref_asserts(dev_priv);
 
        if (ret)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2eff98cdcfade1e70fb63b548ea4258026207318..9a73ea0a32937d2fe9a82bf1a71b8d51d98e70c6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6949,6 +6949,7 @@ enum {
 #define  DISP_FBC_WM_DIS               (1<<15)
 #define DISP_ARB_CTL2  _MMIO(0x45004)
 #define  DISP_DATA_PARTITION_5_6       (1<<6)
+#define  DISP_IPC_ENABLE               (1<<3)
 #define DBUF_CTL       _MMIO(0x45008)
 #define  DBUF_POWER_REQUEST            (1<<31)
 #define  DBUF_POWER_STATE              (1<<30)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5291e08f34369a2d0528a026441da75154a24b76..844efd45fed34750d62da9114b94463fe8b32359 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15255,6 +15255,7 @@ void intel_display_resume(struct drm_device *dev)
        if (!ret)
                ret = __intel_display_resume(dev, state, &ctx);
 
+       intel_enable_ipc(dev_priv);
        drm_modeset_drop_locks(&ctx);
        drm_modeset_acquire_fini(&ctx);
 

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 463ed152e6b1c8523b655156f68a43c8e0eae599..307807672896a74268269d4636535d18e411a02c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1898,6 +1898,8 @@ bool ilk_disable_lp_wm(struct drm_device *dev);
 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
                                  struct intel_crtc_state *cstate);
+void intel_init_ipc(struct drm_i915_private *dev_priv);
+void intel_enable_ipc(struct drm_i915_private *dev_priv);
 static inline int intel_enable_rc6(void)
 {
        return i915.enable_rc6;

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f2911de69ea9a510ecff10d8d1fc1e953891f2e1..fa9055a4f79024df90af0d58a4e2e025de773818 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5824,6 +5824,30 @@ void intel_update_watermarks(struct intel_crtc *crtc)
                dev_priv->display.update_wm(crtc);
 }
 
+void intel_enable_ipc(struct drm_i915_private *dev_priv)
+{
+       u32 val;
+
+       val = I915_READ(DISP_ARB_CTL2);
+
+       if (dev_priv->ipc_enabled)
+               val |= DISP_IPC_ENABLE;
+       else
+               val &= ~DISP_IPC_ENABLE;
+
+       I915_WRITE(DISP_ARB_CTL2, val);
+}
+
+void intel_init_ipc(struct drm_i915_private *dev_priv)
+{
+       dev_priv->ipc_enabled = false;
+       if (!HAS_IPC(dev_priv))
+               return;
+
+       dev_priv->ipc_enabled = true;
+       intel_enable_ipc(dev_priv);
+}
+
 /*
  * Lock protecting IPS related data structures
  */