#pragma weak imx_set_sys_wakeup
#pragma weak imx_noc_slot_config
#pragma weak imx_gpc_handler
+#pragma weak imx_anamix_override
void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint)
{
(0x3f << SLPCR_RBC_COUNT_SHIFT));
}
-struct pll_override {
- uint32_t reg;
- uint32_t override_mask;
-};
-
struct pll_override pll[MAX_PLL_NUM] = {
{.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), },
{.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), },
}
}
+#define MAX_PLL_NUM U(12)
+
+static const struct pll_override imx8mq_pll[MAX_PLL_NUM] = {
+ {.reg = 0x0, .override_mask = 0x140000, },
+ {.reg = 0x8, .override_mask = 0x140000, },
+ {.reg = 0x10, .override_mask = 0x140000, },
+ {.reg = 0x18, .override_mask = 0x140000, },
+ {.reg = 0x20, .override_mask = 0x140000, },
+ {.reg = 0x28, .override_mask = 0x140000, },
+ {.reg = 0x30, .override_mask = 0x1555540, },
+ {.reg = 0x3c, .override_mask = 0x1555540, },
+ {.reg = 0x48, .override_mask = 0x140, },
+ {.reg = 0x54, .override_mask = 0x140, },
+ {.reg = 0x60, .override_mask = 0x140, },
+ {.reg = 0x70, .override_mask = 0xa, },
+};
+
+void imx_anamix_override(bool enter)
+{
+ unsigned int i;
+
+ /* enable the pll override bit before entering DSM mode */
+ for (i = 0; i < MAX_PLL_NUM; i++) {
+ if (enter) {
+ mmio_setbits_32(IMX_ANAMIX_BASE + imx8mq_pll[i].reg,
+ imx8mq_pll[i].override_mask);
+ } else {
+ mmio_clrbits_32(IMX_ANAMIX_BASE + imx8mq_pll[i].reg,
+ imx8mq_pll[i].override_mask);
+ }
+ }
+}
+
int imx_gpc_handler(uint32_t smc_fid,
u_register_t x1,
u_register_t x2,
}
if (is_local_state_off(CLUSTER_PWR_STATE(target_state)))
- imx_set_cluster_powerdown(core_id, true);
+ imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state));
else
imx_set_cluster_standby(true);
if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
imx_set_sys_lpm(core_id, true);
dram_enter_retention();
+ imx_anamix_override(true);
}
}
/* check the system level status */
if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
+ imx_anamix_override(false);
dram_exit_retention();
imx_set_sys_lpm(core_id, false);
imx_clear_rbc_count();
/* check the cluster level power status */
if (is_local_state_off(CLUSTER_PWR_STATE(target_state)))
- imx_set_cluster_powerdown(core_id, false);
+ imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN);
else
imx_set_cluster_standby(false);