riscv: ax25: Andes specific cache shall only support in M-mode

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 68bd4e941956885b0ca0496415dd07a1f88f7dd9..6b4b92e6921612828ba6665a3a9e63ae59f5fb83 100644 (file)
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -14,6 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
        bool "AndeStar V5 families specific cache support"
+       depends on RISCV_MMODE
        help
          Provide Andes Technology AndeStar V5 families specific cache support.