drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7

[WHY]
DISPCLK_MAX_ERRDET_CYCLES must be 7 to prevent connection loss when
changing DENTIST_DISPCLK_WDIVIDER from 126 to 127 and back.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index c961b503b6a1a13f0c889d2add6dd46f9ee51962..f3ac0cf70f687a3b244d13c195cf9d8e187d5252 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -244,7 +244,7 @@ void dcn20_dccg_init(struct dce_hwseq *hws)
        REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 
        /* This value is dependent on the hardware pipeline delay so set once per SOC */
-       REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
+       REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
 }
 
 void dcn20_disable_vga(