This patch is to update the swSMU headers for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
uint8_t NumDfPstatesEnabled;
uint8_t NumDpmLevelsEnabled;
+ uint8_t NumDcfclkLevelsEnabled;
+ uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk
+ uint8_t NumSocClkLevelsEnabled;
+
+ uint8_t IspClkLevelsEnabled; //applies to both ispiclk and ispxclk
+ uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
uint8_t spare[2];
} DpmClocks_t;
#define FEATURE_ATHUB_PG_BIT 56
#define FEATURE_ECO_DEEPCSTATE_BIT 57
#define FEATURE_CC6_BIT 58
-#define NUM_FEATURES 59
+#define FEATURE_GFX_EDC_BIT 59
+#define NUM_FEATURES 60
typedef struct {
// MP1_EXT_SCRATCH0
uint32_t DpmHandlerID : 8;
uint32_t ActivityMonitorID : 8;
uint32_t DpmTimerID : 8;
- uint32_t spare0 : 8;
+ uint32_t DpmHubID : 4;
+ uint32_t DpmHubTask : 4;
// MP1_EXT_SCRATCH1
uint32_t GfxStatus : 2;
uint32_t GfxoffStatus : 8;
uint32_t spare1 : 16;
// MP1_EXT_SCRATCH2
uint32_t P2JobHandler : 32;
- // MP1_EXT_SCRATCH3
-// uint32_t spare2 : 32;
+ // MP1_EXT_SCRATCH3: used for postcodes
+
// MP1_EXT_SCRATCH4:6 are used by Kernel
+ // MP1_EXT_SCRATCH7: used by HW
} FwStatus_t;
#define PPSMC_MSG_StopDramLogging 0x3F
#define PPSMC_MSG_SetSoftMinCclk 0x40
#define PPSMC_MSG_SetSoftMaxCclk 0x41
-#define PPSMC_Message_Count 0x42
+#define PPSMC_MSG_SetDfPstateActiveLevel 0x42
+#define PPSMC_MSG_SetDfPstateSoftMinLevel 0x43
+#define PPSMC_MSG_SetCclkPolicy 0x44
+#define PPSMC_MSG_DramLogSetDramAddrHigh 0x45
+#define PPSMC_MSG_DramLogSetDramBufferSize 0x46
+#define PPSMC_MSG_RequestActiveWgp 0x47
+#define PPSMC_MSG_QueryActiveWgp 0x48
+#define PPSMC_Message_Count 0x49
-//Argument for PPSMC_MSG_GpuChangeState
+//Argument for PPSMC_MSG_GfxDeviceDriverReset
enum {
MODE1_RESET = 1,
MODE2_RESET = 2