drm/i915: check ppgtt validity when init reg state

Check if ppgtt is valid for context when init reg state. For gvt
context which has no i915 allocated ppgtt, failed to check that
would cause kernel null ptr reference error.

v2: remove !48bit ppgtt case as we'll always update before submit (Chris)

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170109131453.3943-1-zhenyuw@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 81665a9eb43f550755cf414fc0bf5c0971db8939..db714dcf92a6b54cd13240204cd9aa102378419f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2103,19 +2103,12 @@ static void execlists_init_reg_state(u32 *reg_state,
        ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
                       0);
 
-       if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
+       if (ppgtt && USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
                /* 64b PPGTT (48bit canonical)
                 * PDP0_DESCRIPTOR contains the base address to PML4 and
                 * other PDP Descriptors are ignored.
                 */
                ASSIGN_CTX_PML4(ppgtt, reg_state);
-       } else {
-               /* 32b PPGTT
-                * PDP*_DESCRIPTOR contains the base address of space supported.
-                * With dynamic page allocation, PDPs may not be allocated at
-                * this point. Point the unallocated PDPs to the scratch page
-                */
-               execlists_update_context_pdps(ppgtt, reg_state);
        }
 
        if (engine->id == RCS) {