fix(imx8m): fix the rank to rank space issue

update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I0fab18cdc378fda760daa0f89c4dd84eb46f7e11

diff --git a/plat/imx/imx8m/ddr/dram.c b/plat/imx/imx8m/ddr/dram.c
index 53605cd71f381b99834d6268d72bd8d555b82c1a..1fea69db80d5fdf6d25877855b2eed6b34a09cca 100644 (file)
--- a/plat/imx/imx8m/ddr/dram.c
+++ b/plat/imx/imx8m/ddr/dram.c
@@ -44,6 +44,25 @@ static void get_mr_values(uint32_t (*mr_value)[8])
        }
 }
 
+static void save_rank_setting(void)
+{
+       uint32_t i, offset;
+       uint32_t pstate_num = dram_info.num_fsp;
+
+       for (i = 0U; i < pstate_num; i++) {
+               offset = i ? (i + 1) * 0x1000 : 0U;
+               dram_info.rank_setting[i][0] = mmio_read_32(DDRC_DRAMTMG2(0) + offset);
+               if (dram_info.dram_type != DDRC_LPDDR4) {
+                       dram_info.rank_setting[i][1] = mmio_read_32(DDRC_DRAMTMG9(0) + offset);
+               }
+#if !defined(PLAT_imx8mq)
+               dram_info.rank_setting[i][2] = mmio_read_32(DDRC_RANKCTL(0) + offset);
+#endif
+       }
+#if defined(PLAT_imx8mq)
+       dram_info.rank_setting[0][2] = mmio_read_32(DDRC_RANKCTL(0));
+#endif
+}
 /* Restore the ddrc configs */
 void dram_umctl2_init(struct dram_timing_info *timing)
 {
@@ -150,6 +169,9 @@ void dram_info_init(unsigned long dram_timing_base)
        }
        dram_info.num_fsp = i;
 
+       /* save the DRAMTMG2/9 for rank to rank workaround */
+       save_rank_setting();
+
        /* check if has bypass mode support */
        if (dram_info.timing_info->fsp_table[idx] < 666) {
                dram_info.bypass_mode = true;

diff --git a/plat/imx/imx8m/ddr/dram_retention.c b/plat/imx/imx8m/ddr/dram_retention.c
index 7d4f8230eb1246aa3f4d8e464dc2f1864afb4e67..96591d18ba8bd5828f4f8b9e94625c1c86dc6613 100644 (file)
--- a/plat/imx/imx8m/ddr/dram_retention.c
+++ b/plat/imx/imx8m/ddr/dram_retention.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018-2022 NXP
+ * Copyright 2018-2023 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -25,6 +25,28 @@
 
 #define DBGCAM_EMPTY           0x36000000
 
+static void rank_setting_update(void)
+{
+       uint32_t i, offset;
+       uint32_t pstate_num = dram_info.num_fsp;
+
+       for (i = 0U; i < pstate_num; i++) {
+               offset = i ? (i + 1) * 0x1000 : 0U;
+               mmio_write_32(DDRC_DRAMTMG2(0) + offset, dram_info.rank_setting[i][0]);
+               if (dram_info.dram_type != DDRC_LPDDR4) {
+                       mmio_write_32(DDRC_DRAMTMG9(0) + offset, dram_info.rank_setting[i][1]);
+               }
+
+#if !defined(PLAT_imx8mq)
+               mmio_write_32(DDRC_RANKCTL(0) + offset,
+                       dram_info.rank_setting[i][2]);
+#endif
+       }
+#if defined(PLAT_imx8mq)
+               mmio_write_32(DDRC_RANKCTL(0), dram_info.rank_setting[0][2]);
+#endif
+}
+
 void dram_enter_retention(void)
 {
        /* Wait DBGCAM to be empty */
@@ -157,6 +179,9 @@ void dram_exit_retention(void)
        /* dram phy re-init */
        dram_phy_init(dram_info.timing_info);
 
+       /* workaround for rank-to-rank issue */
+       rank_setting_update();
+
        /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
        dwc_ddrphy_apb_wr(0xd0000, 0x0);
        while (dwc_ddrphy_apb_rd(0x20097)) {

diff --git a/plat/imx/imx8m/include/dram.h b/plat/imx/imx8m/include/dram.h
index c9f18e80bc064414484ee3b6a359cc5dcb1800df..db433522b55b46a4f1fbceee1d2e3aa333ad6947 100644 (file)
--- a/plat/imx/imx8m/include/dram.h
+++ b/plat/imx/imx8m/include/dram.h
@@ -59,6 +59,8 @@ struct dram_info {
        struct dram_timing_info *timing_info;
        /* mr, emr, emr2, emr3, mr11, mr12, mr22, mr14 */
        uint32_t mr_table[3][8];
+       /* used for workaround for rank to rank issue */
+       uint32_t rank_setting[3][3];
 };
 
 extern struct dram_info dram_info;