MIPS: BPF: Use 32 or 64-bit load instruction to load an address to register

When loading a pointer to register we need to use the appropriate
32 or 64bit instruction to preserve the pointers' top 32bits.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Daniel Borkmann <dborkman@redhat.com>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: netdev@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7180/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c
index 4505e2e6ab53db7f3e5c715f1047a4d6aa8fca32..6e3963425b64cfe753f1df2abaa04d4fc559d630 100644 (file)
--- a/arch/mips/net/bpf_jit.c
+++ b/arch/mips/net/bpf_jit.c
@@ -453,6 +453,17 @@ static inline void emit_wsbh(unsigned int dst, unsigned int src,
        emit_instr(ctx, wsbh, dst, src);
 }
 
+/* load pointer to register */
+static inline void emit_load_ptr(unsigned int dst, unsigned int src,
+                                    int imm, struct jit_ctx *ctx)
+{
+       /* src contains the base addr of the 32/64-pointer */
+       if (config_enabled(CONFIG_64BIT))
+               emit_instr(ctx, ld, dst, imm, src);
+       else
+               emit_instr(ctx, lw, dst, imm, src);
+}
+
 /* load a function pointer to register */
 static inline void emit_load_func(unsigned int reg, ptr imm,
                                  struct jit_ctx *ctx)
@@ -1277,7 +1288,8 @@ jmp_cmp:
                        /* A = skb->dev->ifindex */
                        ctx->flags |= SEEN_SKB | SEEN_A | SEEN_S0;
                        off = offsetof(struct sk_buff, dev);
-                       emit_load(r_s0, r_skb, off, ctx);
+                       /* Load *dev pointer */
+                       emit_load_ptr(r_s0, r_skb, off, ctx);
                        /* error (0) in the delay slot */
                        emit_bcond(MIPS_COND_EQ, r_s0, r_zero,
                                   b_imm(prog->len, ctx), ctx);