refactor(xilinx): rename gic macros to make common

Rename macros PLAT_VERSAL_GICD_BASE, PLAT_VERSAL_GICR_BASE,
PLAT_VERSAL_NET_GICD_BASE and PLAT_VERSAL_NET_GICR_BASE to
PLAT_GICD_BASE_VALUE and PLAT_GICR_BASE_VALUE to make common
for both Versal and Versal NET platforms.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ibcebfb8e741e828ef272b32cbedfb4dcbf8629b6

diff --git a/plat/xilinx/versal/include/plat_macros.S b/plat/xilinx/versal/include/plat_macros.S
index 3a5221225127d620c31d2d10f58ca143342ea29b..f1f9bb7e4a015fbac3b631d86c4b40518f616f62 100644 (file)
--- a/plat/xilinx/versal/include/plat_macros.S
+++ b/plat/xilinx/versal/include/plat_macros.S
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -102,8 +103,8 @@ exit_print_gic_regs:
         * ---------------------------------------------
         */
        .macro plat_crash_print_regs
-       mov_imm x17, PLAT_VERSAL_GICD_BASE
-       mov_imm x16, PLAT_VERSAL_GICR_BASE
+       mov_imm x17, PLAT_GICD_BASE_VALUE
+       mov_imm x16, PLAT_GICR_BASE_VALUE
        versal_print_gic_regs
        .endm
 

diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 6d95fdc5fbca6f5cdfeb6c86881b590404a86a71..e47a6b5994af1e6ba315b5c9a6e41c9dd417e1b3 100644 (file)
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -81,8 +82,8 @@
 #define CACHE_WRITEBACK_SHIFT  6
 #define CACHE_WRITEBACK_GRANULE        (1 << CACHE_WRITEBACK_SHIFT)
 
-#define PLAT_VERSAL_GICD_BASE  U(0xF9000000)
-#define PLAT_VERSAL_GICR_BASE  U(0xF9080000)
+#define PLAT_GICD_BASE_VALUE   U(0xF9000000)
+#define PLAT_GICR_BASE_VALUE   U(0xF9080000)
 
 /*
  * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3

diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index 54f4eb285b533a7405da6b7e813a8d1cb642bf4b..7910d8fc162d740536fef8c755d96ce60ad54f4e 100644 (file)
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -121,7 +122,7 @@ static void pm_client_set_wakeup_sources(uint32_t node_id)
        uint32_t reg_num;
        uint32_t device_id;
        uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX] = { 0U };
-       uintptr_t isenabler1 = PLAT_VERSAL_GICD_BASE + GICD_ISENABLER + 4;
+       uintptr_t isenabler1 = PLAT_GICD_BASE_VALUE + GICD_ISENABLER + 4;
 
        for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
                uint32_t base_irq = reg_num << ISENABLER_SHIFT;

diff --git a/plat/xilinx/versal/versal_gicv3.c b/plat/xilinx/versal/versal_gicv3.c
index 0959c8e942f5cd33a65a7a7b8d61fa5e3140acd4..4f4e0d9db35d35ec2f633528ce886f69f9dab950 100644 (file)
--- a/plat/xilinx/versal/versal_gicv3.c
+++ b/plat/xilinx/versal/versal_gicv3.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -60,8 +61,8 @@ static uint32_t versal_gicv3_mpidr_hash(u_register_t mpidr)
 }
 
 static const gicv3_driver_data_t versal_gic_data __unused = {
-       .gicd_base = PLAT_VERSAL_GICD_BASE,
-       .gicr_base = PLAT_VERSAL_GICR_BASE,
+       .gicd_base = PLAT_GICD_BASE_VALUE,
+       .gicr_base = PLAT_GICR_BASE_VALUE,
        .interrupt_props = versal_interrupt_props,
        .interrupt_props_num = ARRAY_SIZE(versal_interrupt_props),
        .rdistif_num = PLATFORM_CORE_COUNT,

diff --git a/plat/xilinx/versal_net/include/plat_macros.S b/plat/xilinx/versal_net/include/plat_macros.S
index fb108b67c6569cc0f77f91668d281ebd1aac4c14..a0c6604b2ce50ec91fcf42edde2b8d1ddfc5db7f 100644 (file)
--- a/plat/xilinx/versal_net/include/plat_macros.S
+++ b/plat/xilinx/versal_net/include/plat_macros.S
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
  * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -109,8 +109,8 @@ exit_print_gic_regs:
         * Uncomment it when versions are stable
         */
        /*
-       mov_imm x17, PLAT_VERSAL_NET_GICD_BASE
-       mov_imm x16, PLAT_VERSAL_NET_GICR_BASE
+       mov_imm x17, PLAT_GICD_BASE_VALUE
+       mov_imm x16, PLAT_GICR_BASE_VALUE
        versal_net_print_gic_regs
        */
        .endm

diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index 9aa144124b7129a48911b9465bc2fbe8e183fd04..4ce2cc8b51544427eb3d4af5384a398f84d02660 100644 (file)
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
  * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -95,8 +95,8 @@
 #define CACHE_WRITEBACK_SHIFT  U(6)
 #define CACHE_WRITEBACK_GRANULE        (1 << CACHE_WRITEBACK_SHIFT)
 
-#define PLAT_VERSAL_NET_GICD_BASE      U(0xE2000000)
-#define PLAT_VERSAL_NET_GICR_BASE      U(0xE2060000)
+#define PLAT_GICD_BASE_VALUE   U(0xE2000000)
+#define PLAT_GICR_BASE_VALUE   U(0xE2060000)
 
 /*
  * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3

diff --git a/plat/xilinx/versal_net/versal_net_gicv3.c b/plat/xilinx/versal_net/versal_net_gicv3.c
index 138d2c2a6bd24226a3fbedb0ed174858f86b58d2..cee80921c6fdf35558a8010b7b9671583f2bbc85 100644 (file)
--- a/plat/xilinx/versal_net/versal_net_gicv3.c
+++ b/plat/xilinx/versal_net/versal_net_gicv3.c
@@ -63,8 +63,8 @@ static uint32_t versal_net_gicv3_mpidr_hash(u_register_t mpidr)
 }
 
 static const gicv3_driver_data_t versal_net_gic_data __unused = {
-       .gicd_base = PLAT_VERSAL_NET_GICD_BASE,
-       .gicr_base = PLAT_VERSAL_NET_GICR_BASE,
+       .gicd_base = PLAT_GICD_BASE_VALUE,
+       .gicr_base = PLAT_GICR_BASE_VALUE,
        .interrupt_props = versal_net_interrupt_props,
        .interrupt_props_num = ARRAY_SIZE(versal_net_interrupt_props),
        .rdistif_num = PLATFORM_CORE_COUNT,