feat(versal-net): add jtag dcc support

Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC is used as console for
the platform.
Though DCC is not using any UART, VERSAL_NET_UART_BASE needs
to be defined in the platform code. If its not defined, build errors
are observed.
Now VERSAL_NET_UART_BASE by default points to UART0 base.
Check for valid console(pl011, pl011_0, pl011_1, dcc) is
being done in the platform makefile, the error condition in
setting the value of VERSAL_NET_UART_BASE is redundant, thus the error
message is removed from the code.

Change-Id: I1085433055abea13526230cff4d4183ff7a01477
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

diff --git a/docs/plat/xilinx-versal-net.rst b/docs/plat/xilinx-versal-net.rst
index 5d2e663e5e1261e1c414855921b50658ad8e6711..5d0463943061dfeb9aa4a4feae9f72077797b725 100644 (file)
--- a/docs/plat/xilinx-versal-net.rst
+++ b/docs/plat/xilinx-versal-net.rst
@@ -14,6 +14,11 @@ To build:
 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net bl31
 ```
 
+To build TF-A for JTAG DCC console:
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net VERSAL_NET_CONSOLE=dcc bl31
+```
+
 Xilinx Versal NET platform specific build options
 -------------------------------------------------
 
@@ -23,8 +28,9 @@ Xilinx Versal NET platform specific build options
 *   `VERSAL_NET_BL32_MEM_SIZE`: Specifies the size of the memory region of the bl32 binary.
 
 *   `VERSAL_NET_CONSOLE`: Select the console driver. Options:
-    -   `pl011`, `pl011_0`: ARM pl011 UART 0
+    -   `pl011`, `pl011_0`: ARM pl011 UART 0 (default)
     -   `pl011_1`         : ARM pl011 UART 1
+    -   `dcc`             : JTAG Debug Communication Channel(DCC)
 
 *   `TFA_NO_PM` : Platform Management support.
     -    0 : Enable Platform Management (Default)

diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index c9942d6a564c79d460eb1675113c863dda17d16d..2a073b01e113e3c0b77d750d4fea638a401b97b0 100644 (file)
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
  * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,6 +14,7 @@
 #include <common/debug.h>
 #include <common/fdt_fixup.h>
 #include <common/fdt_wrappers.h>
+#include <drivers/arm/dcc.h>
 #include <drivers/arm/pl011.h>
 #include <drivers/console.h>
 #include <lib/mmio.h>
@@ -28,7 +29,6 @@
 
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
-static console_t versal_net_runtime_console;
 
 /*
  * Return a pointer to the 'entry_point_info' structure of the next image for
@@ -95,16 +95,28 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
                panic();
        }
 
-       /* Initialize the console to provide early debug support */
-       rc = console_pl011_register(VERSAL_NET_UART_BASE, uart_clock,
+       if (VERSAL_NET_CONSOLE_IS(pl011_0) || VERSAL_NET_CONSOLE_IS(pl011_1)) {
+               static console_t versal_net_runtime_console;
+
+               /* Initialize the console to provide early debug support */
+               rc = console_pl011_register(VERSAL_NET_UART_BASE, uart_clock,
                                    VERSAL_NET_UART_BAUDRATE,
                                    &versal_net_runtime_console);
-       if (rc == 0) {
-               panic();
-       }
+               if (rc == 0) {
+                       panic();
+               }
 
-       console_set_scope(&versal_net_runtime_console, CONSOLE_FLAG_BOOT |
-                         CONSOLE_FLAG_RUNTIME);
+               console_set_scope(&versal_net_runtime_console, CONSOLE_FLAG_BOOT |
+                               CONSOLE_FLAG_RUNTIME);
+       } else if (VERSAL_NET_CONSOLE_IS(dcc)) {
+               /* Initialize the dcc console for debug.
+                * dcc is over jtag and does not configures uart0 or uart1.
+                */
+               rc = console_dcc_register();
+               if (rc == 0) {
+                       panic();
+               }
+       }
 
        NOTICE("TF-A running on Xilinx %s %d.%d\n", board_name_decode(),
               platform_version / 10U, platform_version % 10U);

diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index 14e63d575e4ce90df3a90a65806885f70774f1de..9d1b7c2782b3324cc41e3c40dd55b67590976865 100644 (file)
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
  * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -24,6 +24,7 @@
 #define VERSAL_NET_CONSOLE_ID_pl011    U(1)
 #define VERSAL_NET_CONSOLE_ID_pl011_0  U(1)
 #define VERSAL_NET_CONSOLE_ID_pl011_1  U(2)
+#define VERSAL_NET_CONSOLE_ID_dcc      U(3)
 
 #define VERSAL_NET_CONSOLE_IS(con)     (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE)
 
@@ -142,12 +143,11 @@
 
 #define VERSAL_NET_UART_BAUDRATE       115200
 
-#if VERSAL_NET_CONSOLE_IS(pl011) || VERSAL_NET_CONSOLE_IS(pl011_0)
-#define VERSAL_NET_UART_BASE           VERSAL_NET_UART0_BASE
-#elif VERSAL_NET_CONSOLE_IS(pl011_1)
+#if VERSAL_NET_CONSOLE_IS(pl011_1)
 #define VERSAL_NET_UART_BASE           VERSAL_NET_UART1_BASE
 #else
-# error "invalid VERSAL_NET_CONSOLE"
+/* Default console is UART0 */
+#define VERSAL_NET_UART_BASE            VERSAL_NET_UART0_BASE
 #endif
 
 #define PLAT_VERSAL_NET_CRASH_UART_BASE                VERSAL_NET_UART_BASE

diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index 622ae98c211613ed734c2fa25c94ee151f2c43e9..28e329519e7395a7d81b3af7f54e8081aa9e4553 100644 (file)
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -53,7 +53,7 @@ USE_COHERENT_MEM := 0
 HW_ASSISTED_COHERENCY := 1
 
 VERSAL_NET_CONSOLE     ?=      pl011
-ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1))
+ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1 dcc))
 else
   $(error Please define VERSAL_NET_CONSOLE)
 endif
@@ -72,6 +72,7 @@ include lib/xlat_tables_v2/xlat_tables.mk
 include lib/libfdt/libfdt.mk
 
 PLAT_BL_COMMON_SOURCES :=      \
+                               drivers/arm/dcc/dcc_console.c                   \
                                drivers/delay_timer/delay_timer.c               \
                                drivers/delay_timer/generic_delay_timer.c       \
                                ${GICV3_SOURCES}                                \