irqchip/gic-v4.1: Add VPE INVALL callback

GICv4.1 redistributors have a VPE-aware INVALL register. Progress!
We can now emulate a guest-requested INVALL without emiting a
VINVALL command.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Link: https://lore.kernel.org/r/20191224111055.11836-14-maz@kernel.org

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 69b16e5da383c5db6ae05d152b4a1c318e751b51..1d8d96a8cc26fc593ad893db9032edf203ce21e0 100644 (file)
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -3669,6 +3669,19 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
        }
 }
 
+static void its_vpe_4_1_invall(struct its_vpe *vpe)
+{
+       void __iomem *rdbase;
+       u64 val;
+
+       val  = GICR_INVALLR_V;
+       val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
+
+       /* Target the redistributor this vPE is currently known on */
+       rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
+       gic_write_lpir(val, rdbase + GICR_INVALLR);
+}
+
 static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
 {
        struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
@@ -3684,6 +3697,7 @@ static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
                return 0;
 
        case INVALL_VPE:
+               its_vpe_4_1_invall(vpe);
                return 0;
 
        default:

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 822dae6abf754fa84c3a82af4ae4b74fddb2bad4..49ed6fa5e29340171c5607234607b14b692927c0 100644 (file)
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -247,6 +247,12 @@
 #define GICR_TYPER_COMMON_LPI_AFF      GENMASK_ULL(25, 24)
 #define GICR_TYPER_AFFINITY            GENMASK_ULL(63, 32)
 
+#define GICR_INVLPIR_VPEID             GENMASK_ULL(47, 32)
+#define GICR_INVLPIR_V                 GENMASK_ULL(63, 63)
+
+#define GICR_INVALLR_VPEID             GICR_INVLPIR_VPEID
+#define GICR_INVALLR_V                 GICR_INVLPIR_V
+
 #define GIC_V3_REDIST_SIZE             0x20000
 
 #define LPI_PROP_GROUP1                        (1 << 1)