]> git.baikalelectronics.ru Git - kernel.git/commitdiff
net: dsa: qca8k: move qca8k read/write/rmw and reg table to common code
authorChristian Marangi <ansuelsmth@gmail.com>
Wed, 27 Jul 2022 11:35:13 +0000 (13:35 +0200)
committerJakub Kicinski <kuba@kernel.org>
Fri, 29 Jul 2022 05:24:38 +0000 (22:24 -0700)
The same reg table and read/write/rmw function are used by drivers
based on qca8k family switch.
Move them to common code to make it accessible also by other drivers.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/dsa/qca/qca8k-8xxx.c
drivers/net/dsa/qca/qca8k-common.c
drivers/net/dsa/qca/qca8k.h

index e9c4a54bc97a7760ea47f7b4f6f9a5485cdcd44e..2c31b7925aae22c3a48427171579e3a6743e1130 100644 (file)
@@ -133,24 +133,6 @@ qca8k_set_page(struct qca8k_priv *priv, u16 page)
        return 0;
 }
 
-static int
-qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
-{
-       return regmap_read(priv->regmap, reg, val);
-}
-
-static int
-qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
-{
-       return regmap_write(priv->regmap, reg, val);
-}
-
-static int
-qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
-{
-       return regmap_update_bits(priv->regmap, reg, mask, write_val);
-}
-
 static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
 {
        struct qca8k_mgmt_eth_data *mgmt_eth_data;
@@ -483,30 +465,6 @@ exit:
        return ret;
 }
 
-static const struct regmap_range qca8k_readable_ranges[] = {
-       regmap_reg_range(0x0000, 0x00e4), /* Global control */
-       regmap_reg_range(0x0100, 0x0168), /* EEE control */
-       regmap_reg_range(0x0200, 0x0270), /* Parser control */
-       regmap_reg_range(0x0400, 0x0454), /* ACL */
-       regmap_reg_range(0x0600, 0x0718), /* Lookup */
-       regmap_reg_range(0x0800, 0x0b70), /* QM */
-       regmap_reg_range(0x0c00, 0x0c80), /* PKT */
-       regmap_reg_range(0x0e00, 0x0e98), /* L3 */
-       regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
-       regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
-       regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
-       regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
-       regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
-       regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
-       regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
-
-};
-
-static const struct regmap_access_table qca8k_readable_table = {
-       .yes_ranges = qca8k_readable_ranges,
-       .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
-};
-
 static struct regmap_config qca8k_regmap_config = {
        .reg_bits = 16,
        .val_bits = 32,
index 7a63e96c8c08f14bc538e14bb1708b8be01d9365..880a49de22b1a1ffaebbb9d8b872fe53b6463981 100644 (file)
@@ -61,3 +61,41 @@ const struct qca8k_mib_desc ar8327_mib[] = {
        MIB_DESC(1, 0xa8, "RXUnicast"),
        MIB_DESC(1, 0xac, "TXUnicast"),
 };
+
+int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
+{
+       return regmap_read(priv->regmap, reg, val);
+}
+
+int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
+{
+       return regmap_write(priv->regmap, reg, val);
+}
+
+int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
+{
+       return regmap_update_bits(priv->regmap, reg, mask, write_val);
+}
+
+static const struct regmap_range qca8k_readable_ranges[] = {
+       regmap_reg_range(0x0000, 0x00e4), /* Global control */
+       regmap_reg_range(0x0100, 0x0168), /* EEE control */
+       regmap_reg_range(0x0200, 0x0270), /* Parser control */
+       regmap_reg_range(0x0400, 0x0454), /* ACL */
+       regmap_reg_range(0x0600, 0x0718), /* Lookup */
+       regmap_reg_range(0x0800, 0x0b70), /* QM */
+       regmap_reg_range(0x0c00, 0x0c80), /* PKT */
+       regmap_reg_range(0x0e00, 0x0e98), /* L3 */
+       regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
+       regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
+       regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
+       regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
+       regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
+       regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
+       regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
+};
+
+const struct regmap_access_table qca8k_readable_table = {
+       .yes_ranges = qca8k_readable_ranges,
+       .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
+};
index 0f274bb350f83c89fdb205ff0cdef9398ec47546..c9b753743dfd936cf597d18828186576e74e425e 100644 (file)
@@ -424,5 +424,11 @@ struct qca8k_fdb {
 
 /* Common setup function */
 extern const struct qca8k_mib_desc ar8327_mib[];
+extern const struct regmap_access_table qca8k_readable_table;
+
+/* Common read/write/rmw function */
+int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val);
+int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val);
+int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val);
 
 #endif /* __QCA8K_H */