drm/amd/display: Fix underflow issue on 175hz timing

[ Upstream commit 735688eb905db529efea0c78466fccc1461c3fde ]

[Why]
Screen underflows happen on 175hz timing for 3 plane overlay case.

[How]
Based on dst y prefetch value clamp to equ or oto for bandwidth
calculation.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Leo Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index b53feeaf5cf117031d531410830292f4dc9306f9..23e4be2ad63f92548db121d34f078ad1ce8991e7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -3454,6 +3454,7 @@ bool dml32_CalculatePrefetchSchedule(
        double TimeForFetchingMetaPTE = 0;
        double TimeForFetchingRowInVBlank = 0;
        double LinesToRequestPrefetchPixelData = 0;
+       double LinesForPrefetchBandwidth = 0;
        unsigned int HostVMDynamicLevelsTrips;
        double  trip_to_mem;
        double  Tvm_trips;
@@ -3883,11 +3884,15 @@ bool dml32_CalculatePrefetchSchedule(
                        TimeForFetchingMetaPTE = Tvm_oto;
                        TimeForFetchingRowInVBlank = Tr0_oto;
                        *PrefetchBandwidth = prefetch_bw_oto;
+                       /* Clamp to oto for bandwidth calculation */
+                       LinesForPrefetchBandwidth = dst_y_prefetch_oto;
                } else {
                        *DestinationLinesForPrefetch = dst_y_prefetch_equ;
                        TimeForFetchingMetaPTE = Tvm_equ;
                        TimeForFetchingRowInVBlank = Tr0_equ;
                        *PrefetchBandwidth = prefetch_bw_equ;
+                       /* Clamp to equ for bandwidth calculation */
+                       LinesForPrefetchBandwidth = dst_y_prefetch_equ;
                }
 
                *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
@@ -3895,7 +3900,7 @@ bool dml32_CalculatePrefetchSchedule(
                *DestinationLinesToRequestRowInVBlank =
                                dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
 
-               LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch -
+               LinesToRequestPrefetchPixelData = LinesForPrefetchBandwidth -
                                *DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank;
 
 #ifdef __DML_VBA_DEBUG__