]> git.baikalelectronics.ru Git - kernel.git/commitdiff
drm/i915/gt: rename legacy engine->hw_id to engine->gen6_hw_id
authorLucas De Marchi <lucas.demarchi@intel.com>
Tue, 20 Jul 2021 23:20:13 +0000 (16:20 -0700)
committerLucas De Marchi <lucas.demarchi@intel.com>
Fri, 23 Jul 2021 00:02:20 +0000 (17:02 -0700)
We kept adding new engines and for that increasing hw_id unnecessarily:
it's not used since GRAPHICS_VER == 8. Prepend "gen6" to the field and
try to pack it in the structs to give a hint this field is actually not
used in recent platforms.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210720232014.3302645-4-lucas.demarchi@intel.com
drivers/gpu/drm/i915/gt/intel_engine_cs.c
drivers/gpu/drm/i915/gt/intel_engine_types.h
drivers/gpu/drm/i915/i915_reg.h

index f720a864142b9dae0a283ffcaa1f189f399c46cf..9c8cba1c6cd1da403cb513f3701d899c0af72839 100644 (file)
@@ -42,7 +42,7 @@
 
 #define MAX_MMIO_BASES 3
 struct engine_info {
-       unsigned int hw_id;
+       u8 gen6_hw_id;
        u8 class;
        u8 instance;
        /* mmio bases table *must* be sorted in reverse graphics_ver order */
@@ -54,7 +54,7 @@ struct engine_info {
 
 static const struct engine_info intel_engines[] = {
        [RCS0] = {
-               .hw_id = RCS0_HW,
+               .gen6_hw_id = RCS0_HW,
                .class = RENDER_CLASS,
                .instance = 0,
                .mmio_bases = {
@@ -62,7 +62,7 @@ static const struct engine_info intel_engines[] = {
                },
        },
        [BCS0] = {
-               .hw_id = BCS0_HW,
+               .gen6_hw_id = BCS0_HW,
                .class = COPY_ENGINE_CLASS,
                .instance = 0,
                .mmio_bases = {
@@ -70,7 +70,7 @@ static const struct engine_info intel_engines[] = {
                },
        },
        [VCS0] = {
-               .hw_id = VCS0_HW,
+               .gen6_hw_id = VCS0_HW,
                .class = VIDEO_DECODE_CLASS,
                .instance = 0,
                .mmio_bases = {
@@ -102,7 +102,7 @@ static const struct engine_info intel_engines[] = {
                },
        },
        [VECS0] = {
-               .hw_id = VECS0_HW,
+               .gen6_hw_id = VECS0_HW,
                .class = VIDEO_ENHANCEMENT_CLASS,
                .instance = 0,
                .mmio_bases = {
@@ -290,7 +290,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
        engine->i915 = i915;
        engine->gt = gt;
        engine->uncore = gt->uncore;
-       engine->hw_id = info->hw_id;
+       engine->gen6_hw_id = info->gen6_hw_id;
        guc_class = engine_class_to_guc_class(info->class);
        engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
        engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
index a107eb58ffa28de3b7cd3ba7b7e4ed12cbd03c4d..266422d8d1b14d73270b851d89936e765d3b5169 100644 (file)
@@ -264,11 +264,11 @@ struct intel_engine_cs {
        enum intel_engine_id id;
        enum intel_engine_id legacy_idx;
 
-       unsigned int hw_id;
        unsigned int guc_id;
 
        intel_engine_mask_t mask;
 
+       u8 gen6_hw_id;
        u8 class;
        u8 instance;
 
index 1022400dd1bd26ffb41180caf1e75179f1dd9dd8..6a2ae109f6116e47bf1adcf1b85aa352eb7d0904 100644 (file)
@@ -2572,7 +2572,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   ARB_MODE_BWGTLB_DISABLE (1 << 9)
 #define   ARB_MODE_SWIZZLE_BDW (1 << 1)
 #define RENDER_HWS_PGA_GEN7    _MMIO(0x04080)
-#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
+#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->gen6_hw_id)
 #define GEN8_RING_FAULT_REG    _MMIO(0x4094)
 #define GEN12_RING_FAULT_REG   _MMIO(0xcec4)
 #define   GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)