drm/amdgpu: add gc 10.3.6 support

this patch adds gc 10.3.6 support.

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 1ba0b055d44be024c33634fe6e61f8d38f24b52e..3501ade93f44571a33ee6bd1f8afb3cfd09a805b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1421,6 +1421,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 7):
                amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
@@ -1559,6 +1560,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
                amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
                break;
        default:
@@ -1765,6 +1767,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(10, 3, 3):
                adev->family = AMDGPU_FAMILY_YC;
                break;
+       case IP_VERSION(10, 3, 6):
+               adev->family = AMDGPU_FAMILY_GC_10_3_6;
+               break;
        case IP_VERSION(10, 3, 7):
                adev->family = AMDGPU_FAMILY_GC_10_3_7;
                break;
@@ -1780,6 +1785,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
        case IP_VERSION(10, 1, 4):
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 3):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 7):
                adev->flags |= AMD_IS_APU;
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 95b8f76d0e7ad702346eacf2d2537f35fba0082e..90158289cd304693451778b0c28ab94f93f6f80b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -106,6 +106,12 @@
 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
+
+#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
+#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
+#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
+#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
+
 #define mmSPI_CONFIG_CNTL_1_Vangogh             0x2441
 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX    1
 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
@@ -258,6 +264,13 @@ MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 
+MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
+MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
+MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
+MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
+MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
+MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
+
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
@@ -3415,6 +3428,32 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] =
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
 };
 
+static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
+{
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
@@ -3678,6 +3717,11 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
                                                golden_settings_gc_10_0_cyan_skillfish,
                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
                break;
+       case IP_VERSION(10, 3, 6):
+               soc15_program_register_sequence(adev,
+                                               golden_settings_gc_10_3_6,
+                                               (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
+               break;
        case IP_VERSION(10, 3, 7):
                soc15_program_register_sequence(adev,
                                                golden_settings_gc_10_3_7,
@@ -3871,6 +3915,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 7):
                adev->gfx.cp_fw_write_wait = true;
@@ -3993,6 +4038,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
        case IP_VERSION(10, 3, 3):
                chip_name = "yellow_carp";
                break;
+       case IP_VERSION(10, 3, 6):
+               chip_name = "gc_10_3_6";
+               break;
        case IP_VERSION(10, 1, 3):
        case IP_VERSION(10, 1, 4):
                if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
@@ -4598,6 +4646,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 7):
                adev->gfx.config.max_hw_contexts = 8;
@@ -4736,6 +4785,7 @@ static int gfx_v10_0_sw_init(void *handle)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 7):
                adev->gfx.me.num_me = 1;
@@ -4975,7 +5025,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
                        bitmap = i * adev->gfx.config.max_sh_per_se + j;
                        if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
-                               (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
+                               (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
+                               (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
                            ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
                                continue;
                        gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -6249,6 +6300,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 7):
                tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
@@ -6387,6 +6439,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
                case IP_VERSION(10, 3, 1):
                case IP_VERSION(10, 3, 4):
                case IP_VERSION(10, 3, 5):
+               case IP_VERSION(10, 3, 6):
                case IP_VERSION(10, 3, 3):
                case IP_VERSION(10, 3, 7):
                        WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
@@ -6402,6 +6455,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
                case IP_VERSION(10, 3, 1):
                case IP_VERSION(10, 3, 4):
                case IP_VERSION(10, 3, 5):
+               case IP_VERSION(10, 3, 6):
                case IP_VERSION(10, 3, 3):
                case IP_VERSION(10, 3, 7):
                        WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
@@ -6501,6 +6555,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
                tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
                tmp &= 0xffffff00;
@@ -7231,6 +7286,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
                break;
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 3):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 7):
                return true;
        default:
@@ -7266,6 +7322,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 7):
                /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
@@ -7587,6 +7644,7 @@ static int gfx_v10_0_soft_reset(void *handle)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
                if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
                        grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
@@ -7654,6 +7712,21 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
                preempt_enable();
                clock = clock_lo | (clock_hi << 32ULL);
                break;
+       case IP_VERSION(10, 3, 6):
+               preempt_disable();
+               clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
+               clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
+               hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
+               /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
+                * roughly every 42 seconds.
+                */
+               if (hi_check != clock_hi) {
+                       clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
+                       clock_hi = hi_check;
+               }
+               preempt_enable();
+               clock = clock_lo | (clock_hi << 32ULL);
+               break;
        default:
                preempt_disable();
                clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
@@ -7719,6 +7792,7 @@ static int gfx_v10_0_early_init(void *handle)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 7):
                adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
@@ -7781,6 +7855,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
                WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 
@@ -7817,6 +7892,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
                WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
                break;
@@ -8271,6 +8347,7 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
                switch (adev->ip_versions[GC_HWIP][0]) {
                case IP_VERSION(10, 3, 1):
                case IP_VERSION(10, 3, 3):
+               case IP_VERSION(10, 3, 6):
                        data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
                        WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
                        break;
@@ -8339,6 +8416,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
                break;
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 3):
+       case IP_VERSION(10, 3, 6):
                gfx_v10_cntl_pg(adev, enable);
                amdgpu_gfx_off_ctrl(adev, enable);
                break;
@@ -8365,6 +8443,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
                gfx_v10_0_update_gfx_clock_gating(adev,
                                                 state == AMD_CG_STATE_GATE);
@@ -9478,6 +9557,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 4):
        case IP_VERSION(10, 3, 5):
+       case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 7):
                adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
@@ -9572,8 +9652,9 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
                        bitmap = i * adev->gfx.config.max_sh_per_se + j;
                        if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
-                               (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
-                               (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
+                            (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
+                            (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
+                            (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
                            ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
                                continue;
                        mask = 1;

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 55fa660e35f4cde01ee85dbafa2dbfc999dc0232..1d65c1fbc4ecc86b088afc9f79d6fabbee0550fa 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -1151,6 +1151,7 @@ struct drm_amdgpu_info_video_caps {
 #define AMDGPU_FAMILY_NV                       143 /* Navi10 */
 #define AMDGPU_FAMILY_VGH                      144 /* Van Gogh */
 #define AMDGPU_FAMILY_YC                       146 /* Yellow Carp */
+#define AMDGPU_FAMILY_GC_10_3_6                        149 /* GC 10.3.6 */
 #define AMDGPU_FAMILY_GC_10_3_7                        151 /* GC 10.3.7 */
 
 #if defined(__cplusplus)