]> git.baikalelectronics.ru Git - uboot.git/commitdiff
arm: dts: k3-j721e-sk: Add initial A72 specific dts support
authorSinthu Raja <sinthu.raja@ti.com>
Wed, 9 Feb 2022 09:36:55 +0000 (15:06 +0530)
committerTom Rini <trini@konsulko.com>
Wed, 16 Feb 2022 19:19:30 +0000 (14:19 -0500)
J721E Starter Kit (SK)[1] is a low cost, small form factor board designed
for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high
performance vision accelerators, video codec accelerators, latest C71x
and C66x DSP, high bandwidth real-time IPs for capture and display, GPU,
dedicated safety island and security accelerators. The SoC is power
optimized to provide best in class performance for industrial and
automotive applications.

    J721E SK supports the following interfaces:
    * 4 GB LPDDR4 RAM
    * x1 Gigabit Ethernet interface
    * x1 USB 3.0 Type-C port
    * x3 USB 3.0 Type-A ports
    * x1 PCIe M.2 E Key
    * x1 PCIe M.2 M Key
    * 512 Mbit OSPI flash
    * x2 CSI2 Camera interface (RPi and TI Camera connector)
    * 40-pin Raspberry Pi GPIO header

Add A72 specific dts for J721E-SK.

[1] https://www.ti.com/tool/SK-TDA4VM

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
arch/arm/dts/Makefile
arch/arm/dts/k3-j721e-sk-u-boot.dtsi [new file with mode: 0644]
arch/arm/dts/k3-j721e-sk.dts [new file with mode: 0644]

index c1cec726cf0f6694bb49742b2c4d3653fc0b8689..4bcccc7364133a4f0c91247f84bc2df066a1139c 100644 (file)
@@ -1139,7 +1139,8 @@ dtb-$(CONFIG_SOC_K3_AM6) += \
 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
                              k3-j721e-r5-common-proc-board.dtb \
                              k3-j7200-common-proc-board.dtb \
-                             k3-j7200-r5-common-proc-board.dtb
+                             k3-j7200-r5-common-proc-board.dtb \
+                             k3-j721e-sk.dtb
 dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb\
                               k3-j721s2-r5-common-proc-board.dtb
 dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi
new file mode 100644 (file)
index 0000000..2d65e2d
--- /dev/null
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+       chosen {
+               stdout-path = "serial2:115200n8";
+               tick-timer = &timer1;
+       };
+
+       aliases {
+               ethernet0 = &cpsw_port1;
+               spi0 = &ospi0;
+               remoteproc0 = &mcu_r5fss0_core0;
+               remoteproc1 = &mcu_r5fss0_core1;
+               remoteproc2 = &main_r5fss0_core0;
+               remoteproc3 = &main_r5fss0_core1;
+               remoteproc4 = &main_r5fss1_core0;
+               remoteproc5 = &main_r5fss1_core1;
+               remoteproc6 = &c66_0;
+               remoteproc7 = &c66_1;
+               remoteproc8 = &c71_0;
+               i2c0 = &wkup_i2c0;
+               i2c1 = &mcu_i2c0;
+               i2c2 = &main_i2c0;
+               mmc1 = &main_sdhci1;  /* SD Card */
+       };
+};
+
+&cbass_main{
+       u-boot,dm-spl;
+
+       main_navss {
+               u-boot,dm-spl;
+       };
+};
+
+&cbass_mcu_wakeup {
+       u-boot,dm-spl;
+
+       timer1: timer@40400000 {
+               compatible = "ti,omap5430-timer";
+               reg = <0x0 0x40400000 0x0 0x80>;
+               ti,timer-alwon;
+               clock-frequency = <25000000>;
+               u-boot,dm-spl;
+       };
+
+       mcu-navss {
+               u-boot,dm-spl;
+
+               ringacc@2b800000 {
+                       reg =   <0x0 0x2b800000 0x0 0x400000>,
+                               <0x0 0x2b000000 0x0 0x400000>,
+                               <0x0 0x28590000 0x0 0x100>,
+                               <0x0 0x2a500000 0x0 0x40000>,
+                               <0x0 0x28440000 0x0 0x40000>;
+                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+                       u-boot,dm-spl;
+               };
+
+               dma-controller@285c0000 {
+                       reg =   <0x0 0x285c0000 0x0 0x100>,
+                               <0x0 0x284c0000 0x0 0x4000>,
+                               <0x0 0x2a800000 0x0 0x40000>,
+                               <0x0 0x284a0000 0x0 0x4000>,
+                               <0x0 0x2aa00000 0x0 0x40000>,
+                               <0x0 0x28400000 0x0 0x2000>;
+                       reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+                                           "tchanrt", "rflow";
+                       u-boot,dm-spl;
+               };
+       };
+
+       chipid@43000014 {
+               u-boot,dm-spl;
+       };
+};
+
+&secure_proxy_main {
+       u-boot,dm-spl;
+};
+
+&dmsc {
+       u-boot,dm-spl;
+       k3_sysreset: sysreset-controller {
+               compatible = "ti,sci-sysreset";
+               u-boot,dm-spl;
+       };
+};
+
+&k3_pds {
+       u-boot,dm-spl;
+};
+
+&k3_clks {
+       u-boot,dm-spl;
+};
+
+&k3_reset {
+       u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+       u-boot,dm-spl;
+};
+
+&main_pmx0 {
+       u-boot,dm-spl;
+};
+
+&main_uart0 {
+       u-boot,dm-spl;
+};
+
+&mcu_uart0 {
+       u-boot,dm-spl;
+};
+
+&main_sdhci0 {
+       status = "disabled";
+};
+
+&main_sdhci1 {
+       u-boot,dm-spl;
+};
+
+&wiz3_pll1_refclk {
+       assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
+       assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
+};
+
+&main_usbss0_pins_default {
+       u-boot,dm-spl;
+};
+
+&usbss0 {
+       u-boot,dm-spl;
+};
+
+&usb0 {
+       dr_mode = "host";
+       u-boot,dm-spl;
+};
+
+&wiz2_pll1_refclk {
+       assigned-clocks = <&wiz2_pll1_refclk>, <&wiz2_pll0_refclk>;
+       assigned-clock-parents = <&k3_clks 294 0>, <&k3_clks 294 11>;
+};
+
+&main_usbss1_pins_default {
+       u-boot,dm-spl;
+};
+
+&usbss1 {
+       u-boot,dm-spl;
+};
+
+&usb1 {
+       dr_mode = "host";
+       u-boot,dm-spl;
+};
+
+&mcu_cpsw {
+       reg = <0x0 0x46000000 0x0 0x200000>,
+             <0x0 0x40f00200 0x0 0x2>;
+       reg-names = "cpsw_nuss", "mac_efuse";
+       /delete-property/ ranges;
+
+       cpsw-phy-sel@40f04040 {
+               compatible = "ti,am654-cpsw-phy-sel";
+               reg= <0x0 0x40f04040 0x0 0x4>;
+               reg-names = "gmii-sel";
+       };
+};
+
+&main_mmc1_pins_default {
+       u-boot,dm-spl;
+};
+
+&wkup_i2c0_pins_default {
+       u-boot,dm-spl;
+};
+
+&wkup_i2c0 {
+       u-boot,dm-spl;
+};
+
+&mcu_i2c0 {
+       u-boot,dm-spl;
+};
+
+&mcu_i2c1 {
+       status = "disabled";
+};
+
+&main_i2c0 {
+       status = "disabled";
+};
+
+&main_i2c1 {
+       status = "disabled";
+};
+
+&main_i2c2 {
+       status = "disabled";
+};
+
+&main_i2c3 {
+       status = "disabled";
+};
+
+&main_i2c4 {
+       status = "disabled";
+};
+
+&main_i2c5 {
+       status = "disabled";
+};
+
+&main_i2c6 {
+       status = "disabled";
+};
+
+&mcu_i2c0_pins_default {
+       u-boot,dm-spl;
+};
+
+&mcu_fss0_ospi0_pins_default {
+       u-boot,dm-spl;
+};
+
+&fss {
+       u-boot,dm-spl;
+};
+
+&ospi0 {
+       u-boot,dm-spl;
+
+       flash@0 {
+               u-boot,dm-spl;
+
+               partition@3fc0000 {
+                       label = "ospi.phypattern";
+                       reg = <0x3fc0000 0x40000>;
+                       u-boot,dm-spl;
+               };
+       };
+};
+
+&serdes_ln_ctrl {
+       u-boot,mux-autoprobe;
+};
+
+&usb_serdes_mux {
+       u-boot,mux-autoprobe;
+};
+
+&pcie0_rc {
+       status = "disabled";
+};
+
+&pcie1_rc {
+       status = "disabled";
+};
+
+&pcie0_ep {
+       status = "disabled";
+};
+
+&pcie1_ep {
+       status = "disabled";
+};
+
+&dss {
+       status = "disabled";
+};
diff --git a/arch/arm/dts/k3-j721e-sk.dts b/arch/arm/dts/k3-j721e-sk.dts
new file mode 100644 (file)
index 0000000..4443cd0
--- /dev/null
@@ -0,0 +1,791 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721e.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+       compatible = "ti,j721e-sk", "ti,j721e";
+       model = "Texas Instruments J721E SK A72";
+
+       chosen {
+               stdout-path = "serial2:115200n8";
+               bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               /* 4G RAM */
+               reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+                     <0x00000008 0x80000000 0x00000000 0x80000000>;
+       };
+
+       reserved_memory: reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               secure_ddr: optee@9e800000 {
+                       reg = <0x00 0x9e800000 0x00 0x01800000>;
+                       alignment = <0x1000>;
+                       no-map;
+               };
+
+               mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa0000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa0100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa1000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa1100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa2000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa2100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa3000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa3100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa4000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa4100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa5000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa5100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa6000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               c66_0_memory_region: c66-memory@a6100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa6100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa7000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               c66_1_memory_region: c66-memory@a7100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa7100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa8000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               c71_0_memory_region: c71-memory@a8100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa8100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               rtos_ipc_memory_region: ipc-memories@aa000000 {
+                       reg = <0x00 0xaa000000 0x00 0x01c00000>;
+                       alignment = <0x1000>;
+                       no-map;
+               };
+       };
+
+       vusb_main: fixedregulator-vusb-main5v0 {
+               /* USB MAIN INPUT 5V DC */
+               compatible = "regulator-fixed";
+               regulator-name = "vusb-main5v0";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       vsys_3v3: fixedregulator-vsys3v3 {
+               /* Output of LM5141 */
+               compatible = "regulator-fixed";
+               regulator-name = "vsys_3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               vin-supply = <&vusb_main>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       vdd_mmc1: fixedregulator-sd {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&vdd_mmc1_en_pins_default>;
+               regulator-name = "vdd_mmc1";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               enable-active-high;
+               vin-supply = <&vsys_3v3>;
+               gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>;
+       };
+
+       vdd_sd_dv_alt: gpio-regulator-tps659411 {
+               compatible = "regulator-gpio";
+               pinctrl-names = "default";
+               pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+               regulator-name = "tps659411";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               vin-supply = <&vsys_3v3>;
+               gpios = <&wkup_gpio0 9 GPIO_ACTIVE_LOW>;
+               states = <3300000 0x0>,
+                        <1800000 0x1>;
+       };
+};
+
+&main_pmx0 {
+       main_mmc1_pins_default: main-mmc1-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+                       J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+                       J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+                       J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+                       J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+                       J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+                       J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+                       J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+               >;
+       };
+
+       main_uart0_pins_default: main-uart0-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
+                       J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
+                       J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+                       J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+               >;
+       };
+
+       main_i2c0_pins_default: main-i2c0-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+                       J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+               >;
+       };
+
+       main_i2c1_pins_default: main-i2c1-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+                       J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+               >;
+       };
+
+       main_i2c3_pins_default: main-i2c3-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+                       J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+               >;
+       };
+
+       mcu_i2c0_pins_default: mcu-i2c0-pins-default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
+                       J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
+               >;
+       };
+
+       main_usbss0_pins_default: main-usbss0-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+                       J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+               >;
+       };
+
+       main_usbss1_pins_default: main-usbss1-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+               >;
+       };
+};
+
+&wkup_pmx0 {
+       mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
+                       J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
+                       J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
+                       J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
+                       J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
+                       J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
+                       J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
+                       J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
+                       J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
+                       J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
+                       J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
+                       J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
+               >;
+       };
+
+       mcu_mdio_pins_default: mcu-mdio1-pins-default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
+                       J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
+               >;
+       };
+
+       mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
+                       J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
+                       J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
+                       J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
+                       J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
+                       J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
+                       J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
+                       J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
+                       J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
+                       J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
+                       J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
+               >;
+       };
+
+       vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
+               >;
+       };
+
+       vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
+               >;
+       };
+
+       wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+                       J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+               >;
+       };
+};
+
+&wkup_uart0 {
+       /* Wakeup UART is used by System firmware */
+       status = "reserved";
+};
+
+&main_uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_uart0_pins_default>;
+       /* Shared with ATF on this platform */
+       power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_uart2 {
+       /* Brought out on RPi header */
+       status = "disabled";
+};
+
+&main_uart3 {
+       /* UART not brought out */
+       status = "disabled";
+};
+
+&main_uart5 {
+       /* UART not brought out */
+       status = "disabled";
+};
+
+&main_uart6 {
+       /* UART not brought out */
+       status = "disabled";
+};
+
+&main_uart7 {
+       /* UART not brought out */
+       status = "disabled";
+};
+
+&main_uart8 {
+       /* UART not brought out */
+       status = "disabled";
+};
+
+&main_uart9 {
+       /* Brought out on M.2 E Key */
+       status = "disabled";
+};
+
+&main_sdhci0 {
+       /* Unused */
+       status = "disabled";
+};
+
+&main_sdhci1 {
+       /* SD Card */
+       vmmc-supply = <&vdd_mmc1>;
+       vqmmc-supply = <&vdd_sd_dv_alt>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_mmc1_pins_default>;
+       ti,driver-strength-ohm = <50>;
+       disable-wp;
+};
+
+&main_sdhci2 {
+       /* Unused */
+       status = "disabled";
+};
+
+&ospi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+       flash@0{
+               compatible = "jedec,spi-nor";
+               reg = <0x0>;
+               spi-tx-bus-width = <8>;
+               spi-rx-bus-width = <8>;
+               spi-max-frequency = <25000000>;
+               cdns,tshsl-ns = <60>;
+               cdns,tsd2d-ns = <60>;
+               cdns,tchsh-ns = <60>;
+               cdns,tslch-ns = <60>;
+               cdns,read-delay = <4>;
+               cdns,phy-mode;
+               cdns,phy-tx-start = <18>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+       };
+};
+
+&ospi1 {
+       /* Unused */
+       status = "disabled";
+};
+
+&main_i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_i2c0_pins_default>;
+       clock-frequency = <400000>;
+};
+
+&main_i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_i2c1_pins_default>;
+       clock-frequency = <400000>;
+};
+
+&main_i2c3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_i2c3_pins_default>;
+       clock-frequency = <400000>;
+};
+
+&main_i2c4 {
+       /* Unused */
+       status = "disabled";
+};
+
+&main_i2c5 {
+       /* Brought out on RPi Header */
+       status = "disabled";
+};
+
+&main_i2c6 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcu_i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_i2c0_pins_default>;
+       clock-frequency = <400000>;
+};
+
+&usb_serdes_mux {
+       idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+};
+
+&serdes_ln_ctrl {
+       idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
+                     <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+                     <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
+                     <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+                     <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+                     <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+       typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+       typec-dir-debounce-ms = <700>;  /* TUSB321, tCCB_DEFAULT 133 ms */
+};
+
+&serdes3 {
+       serdes3_usb_link: link@0 {
+               reg = <0>;
+               cdns,num-lanes = <2>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_USB3>;
+               resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+       };
+};
+
+&usbss0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_usbss0_pins_default>;
+       ti,vbus-divider;
+};
+
+&usb0 {
+       dr_mode = "otg";
+       maximum-speed = "super-speed";
+       phys = <&serdes3_usb_link>;
+       phy-names = "cdns3,usb3-phy";
+};
+
+&serdes2 {
+       serdes2_usb_link: link@1 {
+               reg = <1>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_USB3>;
+               resets = <&serdes_wiz2 2>;
+       };
+};
+
+&usbss1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_usbss1_pins_default>;
+       ti,vbus-divider;
+};
+
+&usb1 {
+       dr_mode = "host";
+       maximum-speed = "super-speed";
+       phys = <&serdes2_usb_link>;
+       phy-names = "cdns3,usb3-phy";
+};
+
+&tscadc0 {
+       /* Unused */
+       status = "disabled";
+};
+
+&tscadc1 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcu_cpsw {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+       };
+};
+
+&cpsw_port1 {
+       phy-mode = "rgmii-rxid";
+       phy-handle = <&phy0>;
+};
+
+&dss {
+       assigned-clocks = <&k3_clks 152 1>,     /* VP 1 pixel clock */
+                         <&k3_clks 152 4>,     /* VP 2 pixel clock */
+                         <&k3_clks 152 9>,     /* VP 3 pixel clock */
+                         <&k3_clks 152 13>;    /* VP 4 pixel clock */
+       assigned-clock-parents = <&k3_clks 152 2>,      /* PLL16_HSDIV0 */
+                                <&k3_clks 152 6>,      /* DPI0_EXT_CLKSEL_OUT0 */
+                                <&k3_clks 152 11>,     /* PLL18_HSDIV0 */
+                                <&k3_clks 152 18>;     /* DPI1_EXT_CLKSEL_OUT0 */
+};
+
+&mcasp0 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcasp1 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcasp2 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcasp3 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcasp4 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcasp5 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcasp6 {
+       /* Brought out on RPi header */
+       status = "disabled";
+};
+
+&mcasp7 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcasp8 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcasp9 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcasp10 {
+       /* Unused */
+       status = "disabled";
+};
+
+&mcasp11 {
+       /* Brought out on M.2 E Key */
+       status = "disabled";
+};
+
+&pcie2_rc {
+       /* Unused */
+       status = "disabled";
+};
+
+&pcie2_ep {
+       /* Unused */
+       status = "disabled";
+};
+
+&pcie3_rc {
+       /* Unused */
+       status = "disabled";
+};
+
+&pcie3_ep {
+       /* Unused */
+       status = "disabled";
+};
+
+&mailbox0_cluster0 {
+       interrupts = <436>;
+
+       mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster1 {
+       interrupts = <432>;
+
+       mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster2 {
+       interrupts = <428>;
+
+       mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster3 {
+       interrupts = <424>;
+
+       mbox_c66_0: mbox-c66-0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_c66_1: mbox-c66-1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster4 {
+       interrupts = <420>;
+
+       mbox_c71_0: mbox-c71-0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+};
+
+&mailbox0_cluster5 {
+       status = "disabled";
+};
+
+&mailbox0_cluster6 {
+       status = "disabled";
+};
+
+&mailbox0_cluster7 {
+       status = "disabled";
+};
+
+&mailbox0_cluster8 {
+       status = "disabled";
+};
+
+&mailbox0_cluster9 {
+       status = "disabled";
+};
+
+&mailbox0_cluster10 {
+       status = "disabled";
+};
+
+&mailbox0_cluster11 {
+       status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+       memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+                       <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+       memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+                       <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+       memory-region = <&main_r5fss0_core0_dma_memory_region>,
+                       <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+       memory-region = <&main_r5fss0_core1_dma_memory_region>,
+                       <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+       memory-region = <&main_r5fss1_core0_dma_memory_region>,
+                       <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+       memory-region = <&main_r5fss1_core1_dma_memory_region>,
+                       <&main_r5fss1_core1_memory_region>;
+};
+
+&c66_0 {
+       mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+       memory-region = <&c66_0_dma_memory_region>,
+                       <&c66_0_memory_region>;
+};
+
+&c66_1 {
+       mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+       memory-region = <&c66_1_dma_memory_region>,
+                       <&c66_1_memory_region>;
+};
+
+&c71_0 {
+       mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+       memory-region = <&c71_0_dma_memory_region>,
+                       <&c71_0_memory_region>;
+};