drm/i915/icl: Update forcewake firmware ranges

Some workarounds are not sticking across suspend resume cycles. The
forcewake ranges table has been updated and would reflect the hardware
appropriately.

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1222
v2: Simplify the table and use 0 for some unused ranges(Matt)

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200416164610.15422-1-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index fa86b7ab2d9960e3ebc0131fe09c004ae27e65cc..078f5b2eb8a4cd36419eca1129b0afd251db207b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1092,8 +1092,7 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
-       GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
-       GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+       GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
        GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
        GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
        GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
@@ -1103,27 +1102,31 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
        GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
        GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
        GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8800, 0x8bff, 0),
        GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
-       GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
-       GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
+       GEN_FW_RANGE(0x9560, 0x95ff, 0),
+       GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER),
        GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
        GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
        GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
        GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
        GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x1a000, 0x243ff, FORCEWAKE_BLITTER),
-       GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24000, 0x2407f, 0),
+       GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
+       GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
+       GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_BLITTER),
        GEN_FW_RANGE(0x40000, 0x1bffff, 0),
        GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
-       GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
-       GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
-       GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
+       GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0),
        GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
-       GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
-       GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
+       GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
 };
 
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */