feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting
sve_supported() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we do SVE specific setup.

Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.

Change-Id: I1caaba2216e8e2a651452254944a003607503216
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

diff --git a/Makefile b/Makefile
index 20b2aa2964da95a856b40fe9f1b988bc753e218f..d2427227cffff0d63c9fe3f1cb4ddad465027553 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1106,7 +1106,6 @@ $(eval $(call assert_booleans,\
         ENABLE_PSCI_STAT \
         ENABLE_RUNTIME_INSTRUMENTATION \
         ENABLE_SME_FOR_SWD \
-        ENABLE_SVE_FOR_NS \
         ENABLE_SVE_FOR_SWD \
         ERROR_DEPRECATED \
         FAULT_INJECTION_SUPPORT \
@@ -1193,6 +1192,7 @@ $(eval $(call assert_numerics,\
         ENABLE_SPE_FOR_NS \
         ENABLE_SYS_REG_TRACE_FOR_NS \
         ENABLE_SME_FOR_NS \
+        ENABLE_SVE_FOR_NS \
         ENABLE_TRF_FOR_NS \
         FW_ENC_STATUS \
         NR_OF_FW_BANKS \

diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 8f3725ad598d662767672edca3e8e74d690b698d..4d151ab45a23984662d3782c52be2fd4667b751a 100644 (file)
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -103,7 +103,7 @@ ifneq (${ENABLE_SME_FOR_NS},0)
 BL31_SOURCES           +=      lib/extensions/sme/sme.c
 BL31_SOURCES           +=      lib/extensions/sve/sve.c
 else
-ifeq (${ENABLE_SVE_FOR_NS},1)
+ifneq (${ENABLE_SVE_FOR_NS},0)
 BL31_SOURCES           +=      lib/extensions/sve/sve.c
 endif
 endif

diff --git a/common/feat_detect.c b/common/feat_detect.c
index 609a38888e1a24ac3e3c0413f53ba69a77d6b54d..9394304bf75b6339534002a3c21c99c9fdbb8931 100644 (file)
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -171,6 +171,8 @@ void detect_arch_features(void)
 
        /* v8.2 features */
        read_feat_ras();
+       check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(),
+                     "SVE", 1, 1);
 
        /* v8.3 features */
        read_feat_pauth();

diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 4483dd424528d6df790c71ff45b36f4b3d078982..1ee07d9ac5ff7c992aaa3f8d05ea3de7df427c3a 100644 (file)
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -428,7 +428,7 @@ Common build options
    mechanism. The default is 2 but is automatically disabled when the target
    architecture is AArch32.
 
--  ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
+-  ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension
    (SVE) for the Non-secure world only. SVE is an optional architectural feature
    for AArch64. Note that when SVE is enabled for the Non-secure world, access
    to SIMD and floating-point functionality from the Secure world is disabled by
@@ -437,9 +437,10 @@ Common build options
    which are aliased by the SIMD and FP registers. The build option is not
    compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
    assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
-   1. The default is 1 but is automatically disabled when ENABLE_SME_FOR_NS=1
-   since SME encompasses SVE. At this time, this build option cannot be used on
-   systems that have SPM_MM enabled.
+   1. This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
+   mechanism. The default is 1 but is automatically disabled when
+   ENABLE_SME_FOR_NS=1 since SME encompasses SVE. At this time, this build
+   option cannot be used on systems that have SPM_MM enabled.
 
 -  ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
    SVE is an optional architectural feature for AArch64. Note that this option

diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index a01dfe7833227a5e24421657ab4c0e17021fbfa3..3ea08a66570677432d9b003e6cfbb98b821b8269 100644 (file)
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -387,10 +387,22 @@ static inline bool is_feat_spe_supported(void)
 /*******************************************************************************
  * Function to identify the presence of FEAT_SVE (Scalable Vector Extension)
  ******************************************************************************/
-static inline bool is_armv8_2_feat_sve_present(void)
+static inline unsigned int read_feat_sve_id_field(void)
 {
-       return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT) &
-               ID_AA64PFR0_SVE_MASK) == ID_AA64PFR0_SVE_SUPPORTED);
+       return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE);
+}
+
+static inline bool is_feat_sve_supported(void)
+{
+       if (ENABLE_SVE_FOR_NS == FEAT_STATE_DISABLED) {
+               return false;
+       }
+
+       if (ENABLE_SVE_FOR_NS == FEAT_STATE_ALWAYS) {
+               return true;
+       }
+
+       return read_feat_sve_id_field() >= ID_AA64PFR0_SVE_SUPPORTED;
 }
 
 /*******************************************************************************

diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h
index 4b66cdb09686244197e3c7a501eb33d5f6d88fee..1faed2d23c080e96a9f2d5a177212ba990d99f88 100644 (file)
--- a/include/lib/extensions/sve.h
+++ b/include/lib/extensions/sve.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,16 @@
 
 #include <context.h>
 
+#if (ENABLE_SME_FOR_NS || ENABLE_SVE_FOR_NS)
 void sve_enable(cpu_context_t *context);
 void sve_disable(cpu_context_t *context);
+#else
+static inline void sve_enable(cpu_context_t *context)
+{
+}
+static inline void sve_disable(cpu_context_t *context)
+{
+}
+#endif /* ( ENABLE_SME_FOR_NS | ENABLE_SVE_FOR_NS ) */
 
 #endif /* SVE_H */

diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 7fbbd8171312a9067f39b9a3b5588493e9bf5dfb..42166eb999c8fcd79cf837c31c475b6a8389ab5c 100644 (file)
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -492,11 +492,10 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
        /* Enable SME, SVE, and FPU/SIMD for non-secure world. */
        if (is_feat_sme_supported()) {
                sme_enable(ctx);
+       } else if (is_feat_sve_supported()) {
+               /* Enable SVE and FPU/SIMD for non-secure world. */
+               sve_enable(ctx);
        }
-#if ENABLE_SVE_FOR_NS
-       /* Enable SVE and FPU/SIMD for non-secure world. */
-       sve_enable(ctx);
-#endif
 
        if (is_feat_mpam_supported()) {
                mpam_enable(el2_unused);
@@ -526,35 +525,38 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
 static void manage_extensions_secure(cpu_context_t *ctx)
 {
 #if IMAGE_BL31
- #if ENABLE_SME_FOR_NS
-  #if ENABLE_SME_FOR_SWD
-       /*
-        * Enable SME, SVE, FPU/SIMD in secure context, secure manager must
-        * ensure SME, SVE, and FPU/SIMD context properly managed.
-        */
-       sme_enable(ctx);
-  #else /* ENABLE_SME_FOR_SWD */
-       /*
-        * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can
-        * safely use the associated registers.
-        */
-       sme_disable(ctx);
-  #endif /* ENABLE_SME_FOR_SWD */
- #elif ENABLE_SVE_FOR_NS
-  #if ENABLE_SVE_FOR_SWD
-       /*
-        * Enable SVE and FPU in secure context, secure manager must ensure that
-        * the SVE and FPU register contexts are properly managed.
-        */
-       sve_enable(ctx);
- #else /* ENABLE_SVE_FOR_SWD */
-       /*
-        * Disable SVE and FPU in secure context so non-secure world can safely
-        * use them.
-        */
-       sve_disable(ctx);
-  #endif /* ENABLE_SVE_FOR_SWD */
- #endif /* ENABLE_SVE_FOR_NS */
+
+       if (is_feat_sme_supported()) {
+               if (ENABLE_SME_FOR_SWD) {
+               /*
+                * Enable SME, SVE, FPU/SIMD in secure context, secure manager
+                * must ensure SME, SVE, and FPU/SIMD context properly managed.
+                */
+                       sme_enable(ctx);
+               } else {
+               /*
+                * Disable SME, SVE, FPU/SIMD in secure context so non-secure
+                * world can safely use the associated registers.
+                */
+                       sme_disable(ctx);
+               }
+       } else if (is_feat_sve_supported()) {
+               if (ENABLE_SVE_FOR_SWD) {
+               /*
+                * Enable SVE and FPU in secure context, secure manager must
+                * ensure that the SVE and FPU register contexts are properly
+                * managed.
+                */
+                       sve_enable(ctx);
+               } else {
+               /*
+                * Disable SVE and FPU in secure context so non-secure world
+                * can safely use them.
+                */
+                       sve_disable(ctx);
+               }
+       }
+
 #endif /* IMAGE_BL31 */
 }
 

diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index 1846e003a833323664da256acd65696626c23aa3..29034fdc4768f06bc1cad0dbf5b7c93e6905ca54 100644 (file)
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -20,13 +20,6 @@ void sme_enable(cpu_context_t *context)
        u_register_t cptr_el3;
        el3_state_t *state;
 
-       /* Make sure SME is implemented in hardware before continuing. */
-       if (!is_feat_sme_supported()) {
-               /* Perhaps the hardware supports SVE only */
-               sve_enable(context);
-               return;
-       }
-
        /* Get the context state. */
        state = get_el3state_ctx(context);
 
@@ -70,13 +63,6 @@ void sme_disable(cpu_context_t *context)
        u_register_t reg;
        el3_state_t *state;
 
-       /* Make sure SME is implemented in hardware before continuing. */
-       if (!is_feat_sme_supported()) {
-               /* Perhaps the hardware supports SVE only */
-               sve_disable(context);
-               return;
-       }
-
        /* Get the context state. */
        state = get_el3state_ctx(context);
 

diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c
index f7dcc767aa252d6030fe0bda39a7095fc2ebabd7..f551ca7e6601826f9440790c311168f3d2f61677 100644 (file)
--- a/lib/extensions/sve/sve.c
+++ b/lib/extensions/sve/sve.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,22 +22,10 @@ CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule);
  */
 #define CONVERT_SVE_LENGTH(x)  (((x / 128) - 1))
 
-static bool sve_supported(void)
-{
-       uint64_t features;
-
-       features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
-       return (features & ID_AA64PFR0_SVE_MASK) == 1U;
-}
-
 void sve_enable(cpu_context_t *context)
 {
        u_register_t cptr_el3;
 
-       if (!sve_supported()) {
-               return;
-       }
-
        cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3);
 
        /* Enable access to SVE functionality for all ELs. */
@@ -54,11 +42,6 @@ void sve_disable(cpu_context_t *context)
        u_register_t reg;
        el3_state_t *state;
 
-       /* Make sure SME is implemented in hardware before continuing. */
-       if (!sve_supported()) {
-               return;
-       }
-
        /* Get the context state. */
        state = get_el3state_ctx(context);
 

diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index ef917f65b17d8a7a574236e4202233ee2c74c6ed..63617b2ae18b3fa9cd2bf0d638056dfa93a8e59f 100644 (file)
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -373,7 +373,7 @@ ENABLE_AMU_FCONF            := 0
 AMU_RESTRICT_COUNTERS          := 0
 
 # Enable SVE for non-secure world by default
-ENABLE_SVE_FOR_NS              := 1
+ENABLE_SVE_FOR_NS              := 2
 # SVE is only supported on AArch64 so disable it on AArch32.
 ifeq (${ARCH},aarch32)
        override ENABLE_SVE_FOR_NS      := 0

diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index e12eae79fc162886c68a251487dd2e9c9b9fdfa3..24f6c412709dfbdae96b9ef2028589ddf071c713 100644 (file)
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -117,19 +117,14 @@ static void rmm_el2_context_init(el2_sysregs_t *regs)
  ******************************************************************************/
 static void manage_extensions_realm(cpu_context_t *ctx)
 {
-#if ENABLE_SVE_FOR_NS
+       if (is_feat_sve_supported()) {
        /*
         * Enable SVE and FPU in realm context when it is enabled for NS.
         * Realm manager must ensure that the SVE and FPU register
         * contexts are properly managed.
         */
-       sve_enable(ctx);
-#else
-       /*
-        * Disable SVE and FPU in realm context when it is disabled for NS.
-        */
-       sve_disable(ctx);
-#endif /* ENABLE_SVE_FOR_NS */
+               sve_enable(ctx);
+       }
 }
 
 /*******************************************************************************

diff --git a/services/std_svc/spm/spm_mm/spm_mm.mk b/services/std_svc/spm/spm_mm/spm_mm.mk
index b1f045ee6bfa961ae2060b86a12d48df72e43245..513e8ef96284a0bf4462524fe6aa5b31b88abceb 100644 (file)
--- a/services/std_svc/spm/spm_mm/spm_mm.mk
+++ b/services/std_svc/spm/spm_mm/spm_mm.mk
@@ -10,7 +10,7 @@ endif
 ifneq (${ARCH},aarch64)
         $(error "Error: SPM_MM is only supported on aarch64.")
 endif
-ifeq (${ENABLE_SVE_FOR_NS},1)
+ifneq (${ENABLE_SVE_FOR_NS},0)
         $(error "Error: SPM_MM is not compatible with ENABLE_SVE_FOR_NS")
 endif
 ifneq (${ENABLE_SME_FOR_NS},0)