drm/i915/display: Implement Wa_16013835468

PSR2 workaround required when mode has delayed vblank.

BSpec: 52890
BSpec: 49421
Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220210185223.95399-2-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 72bd8d3261e0ced0341d0a62c8ee5d79e96f52ff..2e0b092f4b6be52ca0ed5cfb73a4aaeb90a5439f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1063,7 +1063,23 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
        intel_dp->psr.active = true;
 }
 
-static void intel_psr_enable_source(struct intel_dp *intel_dp)
+static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
+{
+       switch (intel_dp->psr.pipe) {
+       case PIPE_A:
+               return LATENCY_REPORTING_REMOVED_PIPE_A;
+       case PIPE_B:
+               return LATENCY_REPORTING_REMOVED_PIPE_B;
+       case PIPE_C:
+               return LATENCY_REPORTING_REMOVED_PIPE_C;
+       default:
+               MISSING_CASE(intel_dp->psr.pipe);
+               return 0;
+       }
+}
+
+static void intel_psr_enable_source(struct intel_dp *intel_dp,
+                                   const struct intel_crtc_state *crtc_state)
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
@@ -1133,6 +1149,20 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
                if (IS_ALDERLAKE_P(dev_priv))
                        intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
                                     CLKGATE_DIS_MISC_DMASC_GATING_DIS);
+
+               /* Wa_16013835468:tgl[b0+], dg1 */
+               if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
+                   IS_DG1(dev_priv)) {
+                       u16 vtotal, vblank;
+
+                       vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal -
+                                crtc_state->uapi.adjusted_mode.crtc_vdisplay;
+                       vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end -
+                                crtc_state->uapi.adjusted_mode.crtc_vblank_start;
+                       if (vblank > vtotal)
+                               intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
+                                            wa_16013835468_bit_get(intel_dp));
+               }
        }
 }
 
@@ -1198,7 +1228,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
        intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
        intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
        intel_psr_enable_sink(intel_dp);
-       intel_psr_enable_source(intel_dp);
+       intel_psr_enable_source(intel_dp, crtc_state);
        intel_dp->psr.enabled = true;
        intel_dp->psr.paused = false;
 
@@ -1297,6 +1327,12 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
                if (IS_ALDERLAKE_P(dev_priv))
                        intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
                                     CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
+
+               /* Wa_16013835468:tgl[b0+], dg1 */
+               if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
+                   IS_DG1(dev_priv))
+                       intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
+                                    wa_16013835468_bit_get(intel_dp), 0);
        }
 
        intel_snps_phy_update_psr_power_state(dev_priv, phy, false);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd78de012f84c3b1a901819019381dbe75c2de01..de403ee18bc70c68f74b9d3cbf6d3ab1e4408d0f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5915,11 +5915,14 @@
 #define HSW_NDE_RSTWRN_OPT     _MMIO(0x46408)
 #define  RESET_PCH_HANDSHAKE_ENABLE    (1 << 4)
 
-#define GEN8_CHICKEN_DCPR_1            _MMIO(0x46430)
-#define   SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
-#define   ICL_DELAY_PMRSP              REG_BIT(22)
-#define   DISABLE_FLR_SRC              REG_BIT(15)
-#define   MASK_WAKEMEM                 REG_BIT(13)
+#define GEN8_CHICKEN_DCPR_1                    _MMIO(0x46430)
+#define   SKL_SELECT_ALTERNATE_DC_EXIT         REG_BIT(30)
+#define   LATENCY_REPORTING_REMOVED_PIPE_C     REG_BIT(25)
+#define   LATENCY_REPORTING_REMOVED_PIPE_B     REG_BIT(24)
+#define   LATENCY_REPORTING_REMOVED_PIPE_A     REG_BIT(23)
+#define   ICL_DELAY_PMRSP                      REG_BIT(22)
+#define   DISABLE_FLR_SRC                      REG_BIT(15)
+#define   MASK_WAKEMEM                         REG_BIT(13)
 
 #define GEN11_CHICKEN_DCPR_2                   _MMIO(0x46434)
 #define   DCPR_MASK_MAXLATENCY_MEMUP_CLR       REG_BIT(27)