drm/i915: Apply Wa_1406680159:icl,ehl as an engine workaround

The register this workaround updates is a render engine register in the
MCR range, so we should initialize this in rcs_engine_wa_init() rather
than gt_wa_init().

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1222
Fixes: d05096fee13c ("drm/i915/icl: Wa_1406680159")
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200311162300.1838847-6-matthew.d.roper@intel.com
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2318b55b97222e809af26c50381d210fb2133667..cbfc8d5ebb3eb531f4ad3609290b40efbdc39b6d 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -920,11 +920,6 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
                            SLICE_UNIT_LEVEL_CLKGATE,
                            MSCUNIT_CLKGATE_DIS);
 
-       /* Wa_1406680159:icl */
-       wa_write_or(wal,
-                   SUBSLICE_UNIT_LEVEL_CLKGATE,
-                   GWUNIT_CLKGATE_DIS);
-
        /* Wa_1406838659:icl (pre-prod) */
        if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
                wa_write_or(wal,
@@ -1487,6 +1482,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                /* Wa_1407352427:icl,ehl */
                wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
                            PSDUNIT_CLKGATE_DIS);
+
+               /* Wa_1406680159:icl,ehl */
+               wa_write_or(wal,
+                           SUBSLICE_UNIT_LEVEL_CLKGATE,
+                           GWUNIT_CLKGATE_DIS);
        }
 
        if (IS_GEN_RANGE(i915, 9, 12)) {