Workaround for Cortex N1 erratum 1946160

Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1.  The workaround is to insert a DMB ST
before acquire atomic instructions without release semantics.  This
issue is present starting from r0p0 but this workaround applies to
revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no
workaround.

SDEN can be found here:
https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index be7096cd3e7d10a26e95c036ded2fc75f558a08d..7c142d132cb5f86735c797d6180f4945f56d3423 100644 (file)
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -310,6 +310,10 @@ For Neoverse N1, the following errata build flags are defined :
 -  ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1
    CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
 
+-  ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1
+   CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
+   revisions r0p0, r1p0, and r2p0 there is no workaround.
+
 DSU Errata Workarounds
 ----------------------
 

diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 96891be1dc714c6c51d067c4f6927b844a5f0a3c..9c97cf60aba6e52b2c1e982adc8a1496fe5fd582 100644 (file)
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -407,6 +407,63 @@ func check_errata_1868343
        b       cpu_rev_var_ls
 endfunc check_errata_1868343
 
+       /* --------------------------------------------------
+        * Errata Workaround for Neoverse N1 Errata #1946160.
+        * This applies to revisions r3p0, r3p1, r4p0, and
+        * r4p1 of Neoverse N1. It also exists in r0p0, r1p0,
+        * and r2p0 but there is no fix in these revisions.
+        * Inputs:
+        * x0: variant[4:7] and revision[0:3] of current cpu.
+        * Shall clobber: x0-x17
+        * --------------------------------------------------
+        */
+func errata_n1_1946160_wa
+       /*
+        * Compare x0 against r3p0 - r4p1
+        */
+       mov     x17, x30
+       bl      check_errata_1946160
+       cbz     x0, 1f
+
+       mov     x0, #3
+       msr     S3_6_C15_C8_0, x0
+       ldr     x0, =0x10E3900002
+       msr     S3_6_C15_C8_2, x0
+       ldr     x0, =0x10FFF00083
+       msr     S3_6_C15_C8_3, x0
+       ldr     x0, =0x2001003FF
+       msr     S3_6_C15_C8_1, x0
+
+       mov     x0, #4
+       msr     S3_6_C15_C8_0, x0
+       ldr     x0, =0x10E3800082
+       msr     S3_6_C15_C8_2, x0
+       ldr     x0, =0x10FFF00083
+       msr     S3_6_C15_C8_3, x0
+       ldr     x0, =0x2001003FF
+       msr     S3_6_C15_C8_1, x0
+
+       mov     x0, #5
+       msr     S3_6_C15_C8_0, x0
+       ldr     x0, =0x10E3800200
+       msr     S3_6_C15_C8_2, x0
+       ldr     x0, =0x10FFF003E0
+       msr     S3_6_C15_C8_3, x0
+       ldr     x0, =0x2001003FF
+       msr     S3_6_C15_C8_1, x0
+
+       isb
+1:
+       ret     x17
+endfunc errata_n1_1946160_wa
+
+func check_errata_1946160
+       /* Applies to r3p0 - r4p1. */
+       mov     x1, #0x30
+       mov     x2, #0x41
+       b       cpu_rev_var_range
+endfunc check_errata_1946160
+
 func neoverse_n1_reset_func
        mov     x19, x30
 
@@ -486,6 +543,11 @@ func neoverse_n1_reset_func
        bl      errata_n1_1868343_wa
 #endif
 
+#if ERRATA_N1_1946160
+       mov     x0, x18
+       bl      errata_n1_1946160_wa
+#endif
+
 #if ENABLE_AMU
        /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
        mrs     x0, actlr_el3
@@ -560,6 +622,7 @@ func neoverse_n1_errata_report
        report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
        report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
        report_errata ERRATA_N1_1868343, neoverse_n1, 1868343
+       report_errata ERRATA_N1_1946160, neoverse_n1, 1946160
        report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
 
        ldp     x8, x30, [sp], #16

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 93b538c580c0352a402dc8f3e7e81e20adb50f72..64a4b4d47db86f0cc761a19ef98cac487cc2d394 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -355,6 +355,11 @@ ERRATA_N1_1542419  ?=0
 # to revision <= r4p0 of the Neoverse N1 cpu.
 ERRATA_N1_1868343      ?=0
 
+# Flag to apply erratum 1946160 workaround during reset. This erratum applies
+# to revisions r3p0, r3p1, r4p0, and r4p1 of the Neoverse N1 cpu.  The issue
+# exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround.
+ERRATA_N1_1946160      ?=0
+
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
 ERRATA_DSU_798953      ?=0
@@ -644,6 +649,10 @@ $(eval $(call add_define,ERRATA_N1_1542419))
 $(eval $(call assert_boolean,ERRATA_N1_1868343))
 $(eval $(call add_define,ERRATA_N1_1868343))
 
+# Process ERRATA_N1_1946160 flag
+$(eval $(call assert_boolean,ERRATA_N1_1946160))
+$(eval $(call add_define,ERRATA_N1_1946160))
+
 # Process ERRATA_DSU_798953 flag
 $(eval $(call assert_boolean,ERRATA_DSU_798953))
 $(eval $(call add_define,ERRATA_DSU_798953))