}
if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
+ amdgpu_gfx_off_ctrl(adev, true);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
} else {
struct amdgpu_device *adev = ring->adev;
atomic_inc(&adev->vcn.total_submission_cnt);
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+
+ if (!cancel_delayed_work_sync(&adev->vcn.idle_work))
+ amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->vcn.vcn_pg_lock);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,