Xilinx changes for v2022.07-rc1 v2
xilinx:
- Allow booting bigger kernels till 100MB
zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device
serial_zynq:
- Change fifo behavior in DEBUG mode
zynq_sdhci:
- Fix BASECLK setting calculation
clk_zynqmp:
- Add support for showing video clock
gpio:
- Update slg driver to handle DT flags
net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver
pwm:
- Add driver for cadence PWM
versal:
- Add support for reserved memory
firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations
include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers
# define PHY_ANEG_TIMEOUT 20000
#endif
- #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
+ #define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024)
-#define CONFIG_CLOCKS
-
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
"fdt_size_r=0x400000\0" \
# define PHY_ANEG_TIMEOUT 20000
#endif
- #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
+ #define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024)
-#define CONFIG_CLOCKS
-
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
"fdt_size_r=0x400000\0" \