| pspeed);
}
-#define ENETC_QOS_ALIGN 64
static int enetc_setup_taprio(struct net_device *ndev,
struct tc_taprio_qopt_offload *admin_conf)
{
struct enetc_cbd cbd = {.cmd = 0};
struct tgs_gcl_conf *gcl_config;
struct tgs_gcl_data *gcl_data;
- dma_addr_t dma, dma_align;
+ dma_addr_t dma;
struct gce *gce;
u16 data_size;
u16 gcl_len;
gcl_config = &cbd.gcl_conf;
data_size = struct_size(gcl_data, entry, gcl_len);
- tmp = dma_alloc_coherent(&priv->si->pdev->dev,
- data_size + ENETC_QOS_ALIGN,
- &dma, GFP_KERNEL);
- if (!tmp) {
- dev_err(&priv->si->pdev->dev,
- "DMA mapping of taprio gate list failed!\n");
+ tmp = enetc_cbd_alloc_data_mem(priv->si, &cbd, data_size,
+ &dma, (void *)&gcl_data);
+ if (!tmp)
return -ENOMEM;
- }
- dma_align = ALIGN(dma, ENETC_QOS_ALIGN);
- gcl_data = (struct tgs_gcl_data *)PTR_ALIGN(tmp, ENETC_QOS_ALIGN);
gce = (struct gce *)(gcl_data + 1);
temp_gce->period = cpu_to_le32(temp_entry->interval);
}
- cbd.length = cpu_to_le16(data_size);
cbd.status_flags = 0;
- cbd.addr[0] = cpu_to_le32(lower_32_bits(dma_align));
- cbd.addr[1] = cpu_to_le32(upper_32_bits(dma_align));
cbd.cls = BDCR_CMD_PORT_GCL;
cbd.status_flags = 0;
ENETC_QBV_PTGCR_OFFSET,
tge & (~ENETC_QBV_TGE));
- dma_free_coherent(&priv->si->pdev->dev, data_size + ENETC_QOS_ALIGN,
- tmp, dma);
+ enetc_cbd_free_data_mem(priv->si, data_size, tmp, &dma);
return err;
}
};
static struct enetc_psfp epsfp = {
+ .dev_bitmap = 0,
.psfp_sfi_bitmap = NULL,
};
struct enetc_cbd cbd = {.cmd = 0};
struct streamid_data *si_data;
struct streamid_conf *si_conf;
- dma_addr_t dma, dma_align;
+ dma_addr_t dma;
u16 data_size;
void *tmp;
int port;
cbd.status_flags = 0;
data_size = sizeof(struct streamid_data);
- tmp = dma_alloc_coherent(&priv->si->pdev->dev,
- data_size + ENETC_QOS_ALIGN,
- &dma, GFP_KERNEL);
- if (!tmp) {
- dev_err(&priv->si->pdev->dev,
- "DMA mapping of stream identify failed!\n");
+ tmp = enetc_cbd_alloc_data_mem(priv->si, &cbd, data_size,
+ &dma, (void *)&si_data);
+ if (!tmp)
return -ENOMEM;
- }
- dma_align = ALIGN(dma, ENETC_QOS_ALIGN);
- si_data = (struct streamid_data *)PTR_ALIGN(tmp, ENETC_QOS_ALIGN);
- cbd.length = cpu_to_le16(data_size);
- cbd.addr[0] = cpu_to_le32(lower_32_bits(dma_align));
- cbd.addr[1] = cpu_to_le32(upper_32_bits(dma_align));
eth_broadcast_addr(si_data->dmac);
si_data->vid_vidm_tg = (ENETC_CBDR_SID_VID_MASK
+ ((0x3 << 14) | ENETC_CBDR_SID_VIDM));
goto out;
/* Enable the entry overwrite again incase space flushed by hardware */
- memset(&cbd, 0, sizeof(cbd));
-
- cbd.index = cpu_to_le16((u16)sid->index);
- cbd.cmd = 0;
- cbd.cls = BDCR_CMD_STREAM_IDENTIFY;
cbd.status_flags = 0;
si_conf->en = 0x80;
memset(si_data, 0, data_size);
- cbd.length = cpu_to_le16(data_size);
-
- cbd.addr[0] = cpu_to_le32(lower_32_bits(dma_align));
- cbd.addr[1] = cpu_to_le32(upper_32_bits(dma_align));
-
/* VIDM default to be 1.
* VID Match. If set (b1) then the VID must match, otherwise
* any VID is considered a match. VIDM setting is only used
err = enetc_send_cmd(priv->si, &cbd);
out:
- dma_free_coherent(&priv->si->pdev->dev, data_size + ENETC_QOS_ALIGN,
- tmp, dma);
+ enetc_cbd_free_data_mem(priv->si, data_size, tmp, &dma);
return err;
}
{
struct enetc_cbd cbd = { .cmd = 2 };
struct sfi_counter_data *data_buf;
- dma_addr_t dma, dma_align;
+ dma_addr_t dma;
u16 data_size;
void *tmp;
int err;
cbd.status_flags = 0;
data_size = sizeof(struct sfi_counter_data);
- tmp = dma_alloc_coherent(&priv->si->pdev->dev,
- data_size + ENETC_QOS_ALIGN,
- &dma, GFP_KERNEL);
- if (!tmp) {
- dev_err(&priv->si->pdev->dev,
- "DMA mapping of stream counter failed!\n");
- return -ENOMEM;
- }
- dma_align = ALIGN(dma, ENETC_QOS_ALIGN);
- data_buf = (struct sfi_counter_data *)PTR_ALIGN(tmp, ENETC_QOS_ALIGN);
-
- cbd.addr[0] = cpu_to_le32(lower_32_bits(dma_align));
- cbd.addr[1] = cpu_to_le32(upper_32_bits(dma_align));
- cbd.length = cpu_to_le16(data_size);
+ tmp = enetc_cbd_alloc_data_mem(priv->si, &cbd, data_size,
+ &dma, (void *)&data_buf);
+ if (!tmp)
+ return -ENOMEM;
err = enetc_send_cmd(priv->si, &cbd);
if (err)
data_buf->flow_meter_dropl;
exit:
- dma_free_coherent(&priv->si->pdev->dev, data_size + ENETC_QOS_ALIGN,
- tmp, dma);
+ enetc_cbd_free_data_mem(priv->si, data_size, tmp, &dma);
return err;
}
struct sgcl_conf *sgcl_config;
struct sgcl_data *sgcl_data;
struct sgce *sgce;
- dma_addr_t dma, dma_align;
+ dma_addr_t dma;
u16 data_size;
int err, i;
void *tmp;
sgcl_config->acl_len = (sgi->num_entries - 1) & 0x3;
data_size = struct_size(sgcl_data, sgcl, sgi->num_entries);
- tmp = dma_alloc_coherent(&priv->si->pdev->dev,
- data_size + ENETC_QOS_ALIGN,
- &dma, GFP_KERNEL);
- if (!tmp) {
- dev_err(&priv->si->pdev->dev,
- "DMA mapping of stream counter failed!\n");
+ tmp = enetc_cbd_alloc_data_mem(priv->si, &cbd, data_size,
+ &dma, (void *)&sgcl_data);
+ if (!tmp)
return -ENOMEM;
- }
- dma_align = ALIGN(dma, ENETC_QOS_ALIGN);
- sgcl_data = (struct sgcl_data *)PTR_ALIGN(tmp, ENETC_QOS_ALIGN);
-
- cbd.length = cpu_to_le16(data_size);
- cbd.addr[0] = cpu_to_le32(lower_32_bits(dma_align));
- cbd.addr[1] = cpu_to_le32(upper_32_bits(dma_align));
sgce = &sgcl_data->sgcl[0];
err = enetc_send_cmd(priv->si, &cbd);
exit:
- dma_free_coherent(&priv->si->pdev->dev, data_size + ENETC_QOS_ALIGN,
- tmp, dma);
-
+ enetc_cbd_free_data_mem(priv->si, data_size, tmp, &dma);
return err;
}