mlxsw: pci: Simplify FRC clock reading

Currently, the reading of FRC values (high and low) is done using macro
which calls to a function. In addition, to calculate the offset of FRC,
a simple macro is used. This code can be simplified by adding an helper
function and calculating the offset explicitly instead of using an
additional macro for that.

Add the helper function and convert the existing code. This helper will be
used later to read UTC clock.

Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c
index 0f452c8dabbd50eb26ff3746ad6aa93e27fb817a..83659fb0559a44fcd7ce932f63ab62e12bf42197 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/pci.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c
@@ -505,6 +505,12 @@ static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
        mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
 }
 
+static unsigned int mlxsw_pci_read32_off(struct mlxsw_pci *mlxsw_pci,
+                                        ptrdiff_t off)
+{
+       return ioread32be(mlxsw_pci->hw_addr + off);
+}
+
 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
                                     struct mlxsw_pci_queue *q,
                                     u16 consumer_counter_limit,
@@ -1809,19 +1815,19 @@ static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
 static u32 mlxsw_pci_read_frc_h(void *bus_priv)
 {
        struct mlxsw_pci *mlxsw_pci = bus_priv;
-       u64 frc_offset;
+       u64 frc_offset_h;
 
-       frc_offset = mlxsw_pci->free_running_clock_offset;
-       return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_H(frc_offset));
+       frc_offset_h = mlxsw_pci->free_running_clock_offset;
+       return mlxsw_pci_read32_off(mlxsw_pci, frc_offset_h);
 }
 
 static u32 mlxsw_pci_read_frc_l(void *bus_priv)
 {
        struct mlxsw_pci *mlxsw_pci = bus_priv;
-       u64 frc_offset;
+       u64 frc_offset_l;
 
-       frc_offset = mlxsw_pci->free_running_clock_offset;
-       return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_L(frc_offset));
+       frc_offset_l = mlxsw_pci->free_running_clock_offset + 4;
+       return mlxsw_pci_read32_off(mlxsw_pci, frc_offset_l);
 }
 
 static const struct mlxsw_bus mlxsw_pci_bus = {

diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
index 543eb8c8a98394387c7291ac4546954f31218f5e..48dbfea0a2a1d5db3fea9050fe55f5ade0efce69 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
@@ -41,9 +41,6 @@
 #define MLXSW_PCI_DOORBELL(offset, type_offset, num)   \
        ((offset) + (type_offset) + (num) * 4)
 
-#define MLXSW_PCI_FREE_RUNNING_CLOCK_H(offset) (offset)
-#define MLXSW_PCI_FREE_RUNNING_CLOCK_L(offset) ((offset) + 4)
-
 #define MLXSW_PCI_CQS_MAX      96
 #define MLXSW_PCI_EQS_COUNT    2
 #define MLXSW_PCI_EQ_ASYNC_NUM 0