CLK: HSDK: CGU: support PLL bypassing

Support setting PLL to bypass mode to support output frequency
equal to input one.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lkml.kernel.org/r/20200311134115.13257-3-Eugeniy.Paltsev@synopsys.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index b47a559f35284187a1bd35f942d85a36d29a3232..0ea7af57a5b1fb3ca4d7580e3aea69797bb5c01b 100644 (file)
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -53,35 +53,37 @@ struct hsdk_pll_cfg {
        u32 fbdiv;
        u32 odiv;
        u32 band;
+       u32 bypass;
 };
 
 static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
-       { 100000000,  0, 11, 3, 0 },
-       { 133000000,  0, 15, 3, 0 },
-       { 200000000,  1, 47, 3, 0 },
-       { 233000000,  1, 27, 2, 0 },
-       { 300000000,  1, 35, 2, 0 },
-       { 333000000,  1, 39, 2, 0 },
-       { 400000000,  1, 47, 2, 0 },
-       { 500000000,  0, 14, 1, 0 },
-       { 600000000,  0, 17, 1, 0 },
-       { 700000000,  0, 20, 1, 0 },
-       { 800000000,  0, 23, 1, 0 },
-       { 900000000,  1, 26, 0, 0 },
-       { 1000000000, 1, 29, 0, 0 },
-       { 1100000000, 1, 32, 0, 0 },
-       { 1200000000, 1, 35, 0, 0 },
-       { 1300000000, 1, 38, 0, 0 },
-       { 1400000000, 1, 41, 0, 0 },
-       { 1500000000, 1, 44, 0, 0 },
-       { 1600000000, 1, 47, 0, 0 },
+       { 100000000,  0, 11, 3, 0, 0 },
+       { 133000000,  0, 15, 3, 0, 0 },
+       { 200000000,  1, 47, 3, 0, 0 },
+       { 233000000,  1, 27, 2, 0, 0 },
+       { 300000000,  1, 35, 2, 0, 0 },
+       { 333000000,  1, 39, 2, 0, 0 },
+       { 400000000,  1, 47, 2, 0, 0 },
+       { 500000000,  0, 14, 1, 0, 0 },
+       { 600000000,  0, 17, 1, 0, 0 },
+       { 700000000,  0, 20, 1, 0, 0 },
+       { 800000000,  0, 23, 1, 0, 0 },
+       { 900000000,  1, 26, 0, 0, 0 },
+       { 1000000000, 1, 29, 0, 0, 0 },
+       { 1100000000, 1, 32, 0, 0, 0 },
+       { 1200000000, 1, 35, 0, 0, 0 },
+       { 1300000000, 1, 38, 0, 0, 0 },
+       { 1400000000, 1, 41, 0, 0, 0 },
+       { 1500000000, 1, 44, 0, 0, 0 },
+       { 1600000000, 1, 47, 0, 0, 0 },
        {}
 };
 
 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
-       { 297000000,  0, 21, 2, 0 },
-       { 540000000,  0, 19, 1, 0 },
-       { 594000000,  0, 21, 1, 0 },
+       { 27000000,   0, 0,  0, 0, 1 },
+       { 297000000,  0, 21, 2, 0, 0 },
+       { 540000000,  0, 19, 1, 0, 0 },
+       { 594000000,  0, 21, 1, 0, 0 },
        {}
 };
 
@@ -134,11 +136,16 @@ static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
 {
        u32 val = 0;
 
-       /* Powerdown and Bypass bits should be cleared */
-       val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
-       val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
-       val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
-       val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
+       if (cfg->bypass) {
+               val = hsdk_pll_read(clk, CGU_PLL_CTRL);
+               val |= CGU_PLL_CTRL_BYPASS;
+       } else {
+               /* Powerdown and Bypass bits should be cleared */
+               val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
+               val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
+               val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
+               val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
+       }
 
        dev_dbg(clk->dev, "write configuration: %#x\n", val);