drm/amd/display: Add DCN3.1 Yellow Carp support to DM

To detect DCN3.1 ASICs and to enable the appropriate number of CRTCs,
pick the right validation paths for display formats and to use the
right DC interfaces.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4f4c6438d24536f28250129ff49a776b746865b7..b9be1ebe419bd540e6bb58d2cb3b70cb97162259 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -109,6 +109,10 @@ MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
+#endif
 
 #define FIRMWARE_RAVEN_DMCU            "amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -1150,6 +1154,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
        case CHIP_VANGOGH:
                init_data.flags.gpu_vm_support = true;
                break;
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       case CHIP_YELLOW_CARP:
+               init_data.flags.gpu_vm_support = true;
+               break;
 #endif
        default:
                break;
@@ -1407,6 +1416,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
        case CHIP_DIMGREY_CAVEFISH:
        case CHIP_BEIGE_GOBY:
        case CHIP_VANGOGH:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       case CHIP_YELLOW_CARP:
+#endif
                return 0;
        case CHIP_NAVI12:
                fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -1525,6 +1537,12 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
                dmub_asic = DMUB_ASIC_DCN303;
                fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
                break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       case CHIP_YELLOW_CARP:
+               dmub_asic = DMUB_ASIC_DCN31;
+               fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
+               break;
+#endif
 
        default:
                /* ASIC doesn't support DMUB. */
@@ -2219,6 +2237,15 @@ static int dm_resume(void *handle)
                                        = 0xffffffff;
                        }
                }
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+               /*
+                * Resource allocation happens for link encoders for newer ASIC in
+                * dc_validate_global_state, so we need to revalidate it.
+                *
+                * This shouldn't fail (it passed once before), so warn if it does.
+                */
+               WARN_ON(dc_validate_global_state(dm->dc, dc_state, false) != DC_OK);
+#endif
 
                WARN_ON(!dc_commit_state(dm->dc, dc_state));
 
@@ -3764,6 +3791,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       case CHIP_YELLOW_CARP:
+#endif
        case CHIP_RENOIR:
                if (register_outbox_irq_handlers(dm->adev)) {
                        DRM_ERROR("DM: Failed to initialize IRQ\n");
@@ -3868,6 +3898,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
        case CHIP_DIMGREY_CAVEFISH:
        case CHIP_BEIGE_GOBY:
        case CHIP_VANGOGH:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       case CHIP_YELLOW_CARP:
+#endif
                if (dcn10_register_irq_handlers(dm->adev)) {
                        DRM_ERROR("DM: Failed to initialize IRQ\n");
                        goto fail;
@@ -4039,6 +4072,13 @@ static int dm_early_init(void *handle)
                adev->mode_info.num_hpd = 6;
                adev->mode_info.num_dig = 6;
                break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+       case CHIP_YELLOW_CARP:
+               adev->mode_info.num_crtc = 4;
+               adev->mode_info.num_hpd = 4;
+               adev->mode_info.num_dig = 4;
+               break;
+#endif
        case CHIP_NAVI14:
        case CHIP_DIMGREY_CAVEFISH:
                adev->mode_info.num_crtc = 5;
@@ -4276,6 +4316,9 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
            adev->asic_type == CHIP_NAVY_FLOUNDER ||
            adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
            adev->asic_type == CHIP_BEIGE_GOBY ||
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+           adev->asic_type == CHIP_YELLOW_CARP ||
+#endif
            adev->asic_type == CHIP_VANGOGH)
                tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
 }
@@ -4695,6 +4738,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
                break;
        case AMDGPU_FAMILY_NV:
        case AMDGPU_FAMILY_VGH:
+       case AMDGPU_FAMILY_YC:
                if (adev->asic_type >= CHIP_SIENNA_CICHLID)
                        add_gfx10_3_modifiers(adev, mods, &size, &capacity);
                else