KVM: x86: Bug the VM if an accelerated x2APIC trap occurs on a "bad" reg

Bug the VM if retrieving the x2APIC MSR/register while processing an
accelerated vAPIC trap VM-Exit fails.  In theory it's impossible for the
lookup to fail as hardware has already validated the register, but bugs
happen, and not checking the result of kvm_lapic_msr_read() would result
in consuming the uninitialized "val" if a KVM or hardware bug occurs.

Fixes: 5e850f11b9e3 ("KVM: x86: Do not block APIC write for non ICR registers")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220804235028.1766253-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index e2ce3556915e95c42ed9a767c9dc1e1376e40b9c..9dda989a1cf0198efceb27086da9416aeac9c128 100644 (file)
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2284,10 +2284,12 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
        struct kvm_lapic *apic = vcpu->arch.apic;
        u64 val;
 
-       if (apic_x2apic_mode(apic))
-               kvm_lapic_msr_read(apic, offset, &val);
-       else
+       if (apic_x2apic_mode(apic)) {
+               if (KVM_BUG_ON(kvm_lapic_msr_read(apic, offset, &val), vcpu->kvm))
+                       return;
+       } else {
                val = kvm_lapic_get_reg(apic, offset);
+       }
 
        /*
         * ICR is a single 64-bit register when x2APIC is enabled.  For legacy