]> git.baikalelectronics.ru Git - uboot.git/commitdiff
riscv: Return to previous privilege level after trap handling
authorBin Meng <bmeng.cn@gmail.com>
Wed, 12 Dec 2018 14:12:43 +0000 (06:12 -0800)
committerAndes <uboot@andestech.com>
Tue, 18 Dec 2018 01:56:27 +0000 (09:56 +0800)
At present the trap handler returns to hardcoded M-mode/S-mode.
Change to returning to previous privilege level instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
arch/riscv/cpu/mtrap.S

index da307e4273bed072e70f75b344ef14a6821cc31f..407ecfa9c07646ddbc556be8802245e233643f04 100644 (file)
@@ -68,14 +68,6 @@ trap_entry:
        jal handle_trap
        csrw MODE_PREFIX(epc), a0
 
-#ifdef CONFIG_RISCV_SMODE
-       /* Remain in S-mode after sret */
-       li t0, SSTATUS_SPP
-#else
-       /* Remain in M-mode after mret */
-       li t0, MSTATUS_MPP
-#endif
-       csrs MODE_PREFIX(status), t0
        LREG x1,   1 * REGBYTES(sp)
        LREG x3,   3 * REGBYTES(sp)
        LREG x4,   4 * REGBYTES(sp)