clk: qcom: support for 2 bit PLL post divider

Current PLL driver only supports 4 bit PLL post divider so
modified the PLL divider operations to support 2 bit PLL
post divider.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 3a38861a79449288ebdfed9150b3230a7d1e06d0..2de66b98e9972be21f3a0a2df412ea3c7f218104 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -45,7 +45,7 @@
 
 #define PLL_USER_CTL(p)                ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
 # define PLL_POST_DIV_SHIFT    8
-# define PLL_POST_DIV_MASK     0xf
+# define PLL_POST_DIV_MASK(p)  GENMASK((p)->width, 0)
 # define PLL_ALPHA_EN          BIT(24)
 # define PLL_ALPHA_MODE                BIT(25)
 # define PLL_VCO_SHIFT         20
@@ -750,7 +750,7 @@ clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
        regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 
        ctl >>= PLL_POST_DIV_SHIFT;
-       ctl &= PLL_POST_DIV_MASK;
+       ctl &= PLL_POST_DIV_MASK(pll);
 
        return parent_rate >> fls(ctl);
 }
@@ -764,13 +764,26 @@ static const struct clk_div_table clk_alpha_div_table[] = {
        { }
 };
 
+static const struct clk_div_table clk_alpha_2bit_div_table[] = {
+       { 0x0, 1 },
+       { 0x1, 2 },
+       { 0x3, 4 },
+       { }
+};
+
 static long
 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
                                 unsigned long *prate)
 {
        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+       const struct clk_div_table *table;
+
+       if (pll->width == 2)
+               table = clk_alpha_2bit_div_table;
+       else
+               table = clk_alpha_div_table;
 
-       return divider_round_rate(hw, rate, prate, clk_alpha_div_table,
+       return divider_round_rate(hw, rate, prate, table,
                                  pll->width, CLK_DIVIDER_POWER_OF_TWO);
 }
 
@@ -784,7 +797,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
        div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
 
        return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
-                                 PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT,
+                                 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
                                  div << PLL_POST_DIV_SHIFT);
 }