select ESBC_HDR_LS if CHAIN_OF_TRUST
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select FSL_TZASC_400
select GICV3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
#elif defined(CONFIG_ARCH_LS1028A)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_FSL_TZASC_400
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
-/* Needed for SPI NOR booting in SPL */
-#define CONFIG_DM_SEQ_ALIAS 1
-
#endif /* __MVEBU_CONFIG_H */
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
#define CFG_MALLOC_F_ADDR 0x00120000
#endif
* GD_FLG_FULL_MALLOC_INIT \
* set \
*/
-
-
-#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SPL_NAND_MXS
-#endif
-
#endif
/* ENET Config */
#define FSL_FSPI_FLASH_NUM 1
#define FSPI0_BASE_ADDR 0x30bb0000
#define FSPI0_AMBA_BASE 0x0
-#define CONFIG_FSPI_QUAD_SUPPORT
-
-#define CONFIG_SYS_FSL_FSPI_AHB
#endif
#ifdef CONFIG_NAND_MXS
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CFG_MALLOC_F_ADDR 0x182000
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CFG_MALLOC_F_ADDR 0x182000
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CFG_MALLOC_F_ADDR 0x182000
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
#define CFG_MALLOC_F_ADDR 0x00120000
#endif
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
#define CFG_MALLOC_F_ADDR 0x00120000
#endif
0x40, 0xd4, 0x5c, 0xca, 0x13, 0x99)
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CFG_MALLOC_F_ADDR 0x182000
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#ifdef CONFIG_SPL_BUILD
-
-#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
-
-#endif /* CONFIG_SPL_BUILD*/
-
#define CFG_SYS_FSL_USDHC_NUM 2
#define CONSOLE_ON_UART1
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CFG_MALLOC_F_ADDR 0x182000