drm/i915/bdw: implement semaphore wait

Semaphore waits use a new instruction, MI_SEMAPHORE_WAIT. The seqno to
wait on is all well defined by the table in the previous patch. There is
nothing else different from previous GEN's semaphore synchronization
code.

v2: Update macros to not require the other ring's ring->id (Chris)

v3: Add missing VCS2 gen8_ring_wait init besides
    s/ring_buffer/engine_cs (Rodrigo)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 218ca7b7bb7c759c96e51f08678afe1ba86dc3a4..8c0f70de9fd726352a8537d3bc2d47735f33c8ef 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -268,6 +268,9 @@
 #define   MI_RESTORE_INHIBIT           (1<<0)
 #define MI_SEMAPHORE_SIGNAL    MI_INSTR(0x1b, 0) /* GEN8+ */
 #define   MI_SEMAPHORE_TARGET(engine)  ((engine)<<15)
+#define MI_SEMAPHORE_WAIT      MI_INSTR(0x1c, 2) /* GEN8+ */
+#define   MI_SEMAPHORE_POLL            (1<<15)
+#define   MI_SEMAPHORE_SAD_GTE_SDD     (1<<12)
 #define MI_STORE_DWORD_IMM     MI_INSTR(0x20, 1)
 #define   MI_MEM_VIRTUAL       (1 << 22) /* 965+ only */
 #define MI_STORE_DWORD_INDEX   MI_INSTR(0x21, 1)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e1aac25fc84c756371efc0e16b869f57a602e540..88196808cc40b0ace446dfb724cf63a89e64d906 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -832,6 +832,31 @@ static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
  * @signaller - ring which has, or will signal
  * @seqno - seqno which the waiter will block on
  */
+
+static int
+gen8_ring_sync(struct intel_engine_cs *waiter,
+              struct intel_engine_cs *signaller,
+              u32 seqno)
+{
+       struct drm_i915_private *dev_priv = waiter->dev->dev_private;
+       int ret;
+
+       ret = intel_ring_begin(waiter, 4);
+       if (ret)
+               return ret;
+
+       intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
+                               MI_SEMAPHORE_GLOBAL_GTT |
+                               MI_SEMAPHORE_SAD_GTE_SDD);
+       intel_ring_emit(waiter, seqno);
+       intel_ring_emit(waiter,
+                       lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
+       intel_ring_emit(waiter,
+                       upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
+       intel_ring_advance(waiter);
+       return 0;
+}
+
 static int
 gen6_ring_sync(struct intel_engine_cs *waiter,
               struct intel_engine_cs *signaller,
@@ -2056,7 +2081,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
                ring->set_seqno = ring_set_seqno;
                if (i915_semaphore_is_enabled(dev)) {
                        WARN_ON(!dev_priv->semaphore_obj);
-                       ring->semaphore.sync_to = gen6_ring_sync;
+                       ring->semaphore.sync_to = gen8_ring_sync;
                        ring->semaphore.signal = gen8_rcs_signal;
                        GEN8_RING_SEMAPHORE_INIT;
                }
@@ -2267,7 +2292,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
                        ring->dispatch_execbuffer =
                                gen8_ring_dispatch_execbuffer;
                        if (i915_semaphore_is_enabled(dev)) {
-                               ring->semaphore.sync_to = gen6_ring_sync;
+                               ring->semaphore.sync_to = gen8_ring_sync;
                                ring->semaphore.signal = gen8_xcs_signal;
                                GEN8_RING_SEMAPHORE_INIT;
                        }
@@ -2343,8 +2368,8 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
        ring->irq_put = gen8_ring_put_irq;
        ring->dispatch_execbuffer =
                        gen8_ring_dispatch_execbuffer;
-       ring->semaphore.sync_to = gen6_ring_sync;
        if (i915_semaphore_is_enabled(dev)) {
+               ring->semaphore.sync_to = gen8_ring_sync;
                ring->semaphore.signal = gen8_xcs_signal;
                GEN8_RING_SEMAPHORE_INIT;
        }
@@ -2374,7 +2399,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
                ring->irq_put = gen8_ring_put_irq;
                ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
                if (i915_semaphore_is_enabled(dev)) {
-                       ring->semaphore.sync_to = gen6_ring_sync;
+                       ring->semaphore.sync_to = gen8_ring_sync;
                        ring->semaphore.signal = gen8_xcs_signal;
                        GEN8_RING_SEMAPHORE_INIT;
                }
@@ -2432,7 +2457,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
                ring->irq_put = gen8_ring_put_irq;
                ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
                if (i915_semaphore_is_enabled(dev)) {
-                       ring->semaphore.sync_to = gen6_ring_sync;
+                       ring->semaphore.sync_to = gen8_ring_sync;
                        ring->semaphore.signal = gen8_xcs_signal;
                        GEN8_RING_SEMAPHORE_INIT;
                }