arm64: Add decoding macros for CP15_32 and CP15_64 traps

So far, we don't have anything to help decoding ESR_ELx when dealing
with ESR_ELx_EC_CP15_{32,64}. As we're about to handle some of those,
let's add some useful macros.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 37e84f277ee2e8167d49a05859d4c31e0c70e258..56d32e5557a5e9c6512ce5b0957d6ca4697fe2f1 100644 (file)
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -263,6 +263,58 @@
 
 #define ESR_ELx_FP_EXC_TFV     (UL(1) << 23)
 
+/*
+ * ISS field definitions for CP15 accesses
+ */
+#define ESR_ELx_CP15_32_ISS_DIR_MASK   0x1
+#define ESR_ELx_CP15_32_ISS_DIR_READ   0x1
+#define ESR_ELx_CP15_32_ISS_DIR_WRITE  0x0
+
+#define ESR_ELx_CP15_32_ISS_RT_SHIFT   5
+#define ESR_ELx_CP15_32_ISS_RT_MASK    (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
+#define ESR_ELx_CP15_32_ISS_CRM_SHIFT  1
+#define ESR_ELx_CP15_32_ISS_CRM_MASK   (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
+#define ESR_ELx_CP15_32_ISS_CRN_SHIFT  10
+#define ESR_ELx_CP15_32_ISS_CRN_MASK   (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
+#define ESR_ELx_CP15_32_ISS_OP1_SHIFT  14
+#define ESR_ELx_CP15_32_ISS_OP1_MASK   (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
+#define ESR_ELx_CP15_32_ISS_OP2_SHIFT  17
+#define ESR_ELx_CP15_32_ISS_OP2_MASK   (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
+
+#define ESR_ELx_CP15_32_ISS_SYS_MASK   (ESR_ELx_CP15_32_ISS_OP1_MASK | \
+                                        ESR_ELx_CP15_32_ISS_OP2_MASK | \
+                                        ESR_ELx_CP15_32_ISS_CRN_MASK | \
+                                        ESR_ELx_CP15_32_ISS_CRM_MASK | \
+                                        ESR_ELx_CP15_32_ISS_DIR_MASK)
+#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
+                                       (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
+                                        ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
+                                        ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
+                                        ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
+
+#define ESR_ELx_CP15_64_ISS_DIR_MASK   0x1
+#define ESR_ELx_CP15_64_ISS_DIR_READ   0x1
+#define ESR_ELx_CP15_64_ISS_DIR_WRITE  0x0
+
+#define ESR_ELx_CP15_64_ISS_RT_SHIFT   5
+#define ESR_ELx_CP15_64_ISS_RT_MASK    (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
+
+#define ESR_ELx_CP15_64_ISS_RT2_SHIFT  10
+#define ESR_ELx_CP15_64_ISS_RT2_MASK   (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
+
+#define ESR_ELx_CP15_64_ISS_OP1_SHIFT  16
+#define ESR_ELx_CP15_64_ISS_OP1_MASK   (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
+#define ESR_ELx_CP15_64_ISS_CRM_SHIFT  1
+#define ESR_ELx_CP15_64_ISS_CRM_MASK   (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
+
+#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
+                                       (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
+                                        ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
+
+#define ESR_ELx_CP15_64_ISS_SYS_MASK   (ESR_ELx_CP15_64_ISS_OP1_MASK | \
+                                        ESR_ELx_CP15_64_ISS_CRM_MASK | \
+                                        ESR_ELx_CP15_64_ISS_DIR_MASK)
+
 #ifndef __ASSEMBLY__
 #include <asm/types.h>