.tlv_count = 20,
},
.endpoint = {
- .seq_type = IPA_SEQ_DMA,
.config = {
.resource_group = 0,
.dma_mode = true,
.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
+ .tx = {
+ .seq_type = IPA_SEQ_DMA,
+ },
},
},
},
.tlv_count = 6,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
- .seq_rep_type = IPA_SEQ_REP_INVALID,
.config = {
.resource_group = 0,
.aggregation = true,
},
.endpoint = {
.filter_support = true,
- .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC,
- .seq_rep_type = IPA_SEQ_REP_DMA_PARSER,
.config = {
.resource_group = 0,
.checksum = true,
.qmap = true,
.status_enable = true,
.tx = {
+ .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC,
+ .seq_rep_type = IPA_SEQ_REP_DMA_PARSER,
.status_endpoint =
IPA_ENDPOINT_MODEM_AP_RX,
},
.tlv_count = 6,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
- .seq_rep_type = IPA_SEQ_REP_INVALID,
.config = {
.resource_group = 0,
.checksum = true,
.tlv_count = 20,
},
.endpoint = {
- .seq_type = IPA_SEQ_DMA,
.config = {
.resource_group = 1,
.dma_mode = true,
.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
+ .tx = {
+ .seq_type = IPA_SEQ_DMA,
+ },
},
},
},
.tlv_count = 8,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
- .seq_rep_type = IPA_SEQ_REP_INVALID,
.config = {
.resource_group = 1,
.aggregation = true,
},
.endpoint = {
.filter_support = true,
- .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
.config = {
.resource_group = 1,
.checksum = true,
.qmap = true,
.status_enable = true,
.tx = {
+ .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
.status_endpoint =
IPA_ENDPOINT_MODEM_AP_RX,
},
.tlv_count = 8,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
- .seq_rep_type = IPA_SEQ_REP_INVALID,
.config = {
.resource_group = 1,
.checksum = true,
/**
* struct ipa_endpoint_tx_data - configuration data for TX endpoints
+ * @seq_type: primary packet processing sequencer type
+ * @seq_rep_type: sequencer type for replication processing
* @status_endpoint: endpoint to which status elements are sent
*
* The @status_endpoint is only valid if the endpoint's @status_enable
* flag is set.
*/
struct ipa_endpoint_tx_data {
+ enum ipa_seq_type seq_type;
+ enum ipa_seq_rep_type seq_rep_type;
enum ipa_endpoint_name status_endpoint;
};
/**
* struct ipa_endpoint_data - IPA endpoint configuration data
* @filter_support: whether endpoint supports filtering
- * @seq_type: primary packet processing sequencer type
- * @seq_rep_type: sequencer type for replication processing
* @config: hardware configuration (see above)
*
* Not all endpoints support the IPA filtering capability. A filter table
* in the system, and indicate whether they support filtering.
*
* The remaining endpoint configuration data applies only to AP endpoints.
- * The IPA hardware is implemented by sequencers, and the AP must program
- * the type(s) of these sequencers at initialization time. The remaining
- * endpoint configuration data is defined above.
*/
struct ipa_endpoint_data {
bool filter_support;
- /* The next three are specified only for AP endpoints */
- enum ipa_seq_type seq_type;
- enum ipa_seq_rep_type seq_rep_type;
+ /* Everything else is specified only for AP endpoints */
struct ipa_endpoint_config_data config;
};
return; /* Register not valid for RX endpoints */
/* Low-order byte configures primary packet processing */
- val |= u32_encode_bits(endpoint->seq_type, SEQ_TYPE_FMASK);
+ val |= u32_encode_bits(endpoint->data->tx.seq_type, SEQ_TYPE_FMASK);
/* Second byte configures replicated packet processing */
- val |= u32_encode_bits(endpoint->seq_rep_type, SEQ_REP_TYPE_FMASK);
+ val |= u32_encode_bits(endpoint->data->tx.seq_rep_type,
+ SEQ_REP_TYPE_FMASK);
iowrite32(val, endpoint->ipa->reg_virt + offset);
}
endpoint->ipa = ipa;
endpoint->ee_id = data->ee_id;
- endpoint->seq_type = data->endpoint.seq_type;
- endpoint->seq_rep_type = data->endpoint.seq_rep_type;
endpoint->channel_id = data->channel_id;
endpoint->endpoint_id = data->endpoint_id;
endpoint->toward_ipa = data->toward_ipa;
*/
struct ipa_endpoint {
struct ipa *ipa;
- enum ipa_seq_type seq_type;
- enum ipa_seq_rep_type seq_rep_type;
enum gsi_ee_id ee_id;
u32 channel_id;
u32 endpoint_id;
IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06,
IPA_SEQ_2_PASS = 0x0a,
IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c,
- IPA_SEQ_INVALID = 0x0c,
};
/**
*/
enum ipa_seq_rep_type {
IPA_SEQ_REP_DMA_PARSER = 0x08,
- IPA_SEQ_REP_INVALID = 0x0c,
};
#define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \