arm: dts: armada8040: Fix CP0 eMMC/SDIO support

During the migration to a single DTSI for the CP110-s specific pinctrl
compatibles were moved to the SoC DTSI as CP0 and CP1 have some specifics.
Namely, CP0 eMMC/SDIO support depends on the mvebu-pinctrl driver setting
the BIT(0) in eMMC PHY IO Control 0 Register to 0 in order for the connect
the eMMC/SDIO PHY to the controller and not use it as a MPP pin multiplexor.

So, the mvebu-pinctrl driver check specifically for the
"marvell,armada-8k-cpm-pinctrl" compatible to clear the that bit.

Issue is that compatibles in the 8040 DTSI were set to "marvell,8k-cpm-pinctrl"
for CP0 and "marvell,8k-cps-pinctrl" for the CP1.
This is obviously incorrect as the pinctrl driver does not know about these.

So fix the regression by applying correct compatibles to the DTSI.
Regression found and tested on the Puzzle M801 board.

Fixes: fe9f65f8 ("arm: armada: dts: Use a single dtsi for cp110 die description")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi
index 5123742b8d511c5a4d48ec275dcaa03080515ca3..eec5fa2774057d9365c3a42cfa846a3620cad1ce 100644 (file)
--- a/arch/arm/dts/armada-8040.dtsi
+++ b/arch/arm/dts/armada-8040.dtsi
@@ -40,7 +40,7 @@
 };
 
 &cp0_pinctl {
-       compatible = "marvell,mvebu-pinctrl", "marvell,8k-cpm-pinctrl";
+       compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
        bank-name ="cp0-110";
 
        cp0_i2c0_pins: cp0-i2c-pins-0 {
@@ -75,7 +75,7 @@
 };
 
 &cp1_pinctl {
-       compatible = "marvell,mvebu-pinctrl", "marvell,8k-cps-pinctrl";
+       compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cps-pinctrl";
        bank-name ="cp1-110";
 
        cp1_ge1_rgmii_pins: cp1-ge-rgmii-pins-0 {